相关论文: Nanoscale SOI-MOSFETs with Electrically Induced So…

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed…

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the…

Field-effect transistors (FETs) with single gates are adversely affected by short channel effects such as drain-induced barrier lowering (DIBL) and increases in the magnitude of sub-threshold swing as the channel length is reduced.…

The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET…

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier…

We have used a simple, analytically solvable model to analyze the characteristic s of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10-nm-scale channel length L. The model assumes ballistic dynamics of 2D…

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…

Most carbon nanotube field-effect transistors (CNTFETs) directly attach metal source/drain contacts to an intrinsic nanotube channel. When the gate oxide thickness is reduced, such transistors display strong ambipolar conduction, even when…

While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an…

Scaling transistors' dimensions has been the thrust for the semiconductor industry in the last 4 decades. However, scaling channel lengths beyond 10 nm has become exceptionally challenging due to the direct tunneling between source and…

We report a strategy to design nanoscale cold-source field-effect transistors (CS-FETs) with bias-independent sub-60 mV/dec subthreshold swing (SS). By first-principles calculations and quantum-transport simulations, we reveal that the…

Using local scanning electrical techniques we study edge effects in side-gated Hall nanodevices made of epitaxial graphene. We demonstrate that lithographically defined edges of the graphene channel exhibit hole conduction within the narrow…

We have presented a compact MOSFET model, which allows us to describe the I-V characteristics of irradiated long-channel and short-channel transistors in all operation modes at different measurement temperatures and interface trap…

We have experimentally and theoretically investigated the electron spin transport and spin distribution at room temperature in a Si two-dimensional (2D) inversion channel of back-gate-type spin metal-oxide-semiconductor field-effect…

We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a…

A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at…

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an…

Spin-based metal-oxide-semiconductor field-effect transistors (MOSFET) with a high-mobility III-V channel are studied using self-consistent quantum corrected ensemble Monte Carlo device simulations of charge and spin transport. The…

In this paper, we propose a new trench power MOSFET with strained Si channel that provides lower on resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si1-xGex body with a compositionally graded Si1-xGex…