相关论文: Performance Analysis of a Ge/Si Core/Shell Nanowir…

The ballistic performance of electron transport in nanowire transistors is examined using a 10 orbital sp3d5s* atomistic tight-binding model for the description of the electronic structure, and the top-of-the-barrier semiclassical ballistic…

In this letter, we explore the bandstructure effects on the performance of ballistic silicon nanowire transistors (SNWTs). The energy dispersion relations for silicon nanowires are evaluated with an sp3d5s* tight binding model. Based on the…

We study ballistic hole transport through Ge/Si core/shell nanowires at low temperatures. We observe Fabry-P$\acute{e}$rot interference patterns as well as conductance plateaus at integer multiples of 2e$^2$/h at zero magnetic field.…

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with…

Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature.…

We investigated the electronic properties of strained Si/Ge core-shell nanowires along the [110] direction using first principles calculations based on density-functional theory. The diameter of the studied core-shell wire is up to 5 nm. We…

Semiconducting single-walled carbon nanotubes are studied in the diffusive transport regime. The peak mobility is found to scale with the square of the nanotube diameter and inversely with temperature. The maximum conductance, corrected for…

We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions…

We investigate the transport characteristics of Ge/Si-Core/Shell nanowire with Coulomb Blockade in presence of external magneto-electric fields from a theoretical basis. Using the effective Luttinger-Kohn Hamiltonian we calculate the…

Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors…

Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time; thereby removing uncertainties in calculated mobility…

We have simultaneously measured conductance and thermoelectric power (TEP) of individual silicon and germanium/silicon core/shell nanowires in the field effect transistor device configuration. As the applied gate voltage changes, the TEP…

A 20 band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to theoretically examine the bandstructure carrier velocity and…

As a result of suppressed phonon conduction, large improvements of the thermoelectric figure of merit, ZT, have been recently reported for nanostructures compared to the raw materials' ZT values. It has also been suggested that low…

We study the low-temperature electron mobility of InSb nanowires. We extract the mobility at 4.2 Kelvin by means of field effect transport measurements using a model consisting of a nanowire-transistor with contact resistances. This model…

Strain engineering in semiconductor nanostructures offers a promising route to optimize electronic and optical properties for advanced quantum technologies. This study explores the relationship between core and shell thicknesses and strain…

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…

Using a one-dimensional tight-binding Anderson model, we study a disordered nanowire in the presence of an external gate which can be used for depleting its carrier density (field effect transistor device configuration). In this first…

Low dimensional materials provide the possibility of improved thermoelectric performance due to the additional length scale degree of freedom for engineering their electronic and thermal properties. As a result of suppressed phonon…

We theoretically investigate nonlinear ballistic thermoelectric transport in a superlattice-structured nanowire. By a special choice of nonuniform widths of the superlattice barriers - analogous to anti-reflection coating in optical systems…