相关论文: Gate Electrostatic Controllability Enhancement in …

The atomic-level structural detail and the quantum effects are becoming crucial to device performance as the emerging advanced transistors, representatively GAAFETs, are scaling down towards sub-3nm nodes. However, a multiscale simulation…

In this paper, we propose the application of a Dual Material Gate (DMG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average…

Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive…

In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor…

Carbon Nanotube (CNT) is one of the most significant materials for the development of faster and improved performance of nano-scaled transistors. This paper aims at analyzing a trade-off between device performance and device size of CNT…

We develop a robust and versatile platform to define nanostructures at oxide interfaces via patterned top gates. Using LaAlO$_3$/SrTiO$_3$ as a model system, we demonstrate controllable electrostatic confinement of electrons to nanoscale…

We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned…

Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…

In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from…

Short channel (~80 nm) n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) with potassium (K) doped source and drain regions and high-k gate dielectrics (ALD HfO2) are obtained. For nanotubes with diameter ~ 1.6 nm…

We have used a simple, analytically solvable model to analyze the characteristic s of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10-nm-scale channel length L. The model assumes ballistic dynamics of 2D…

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier…

In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…

In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very…

Bottom-up synthesized GNRs and GNR heterostructures have promising electronic properties for high performance field effect transistors (FETs) and ultra-low power devices such as tunnelling FETs. However, the short length and wide band gap…

We propose and analyze a novel dual-gate Spin Field Effect Transistor (SpinFET) with half-metallic ferromagnetic source and drain contacts. The transistor has two gate pads that can be biased independently. It can be switched ON or OFF with…

Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature.…

The ability to tune material properties using gate electric field is at the heart of modern electronic technology. It is also a driving force behind recent advances in two-dimensional systems, such as gate-electric-field induced…

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current…

Low-dimensional materials such as layered semiconductors or carbon nanotubes (CNTs) have been attracting increasing attention in the last decades due to their inherent scaling properties, which become fundamental to sustain the scaling in…