相关论文: The Investigation of Negative Capacitance Vertical…

In this study, a model of a Schottky-barrier carbon nanotube field- effect transistor (CNT-FET), with ferromagnetic contacts, has been developed. The emphasis is put on analysis of current-voltage characteristics as well as shot (and…

In this work, we analyze the ferroelectric (FE) domain-wall (DW) induced negative capacitance (NC) effect in Metal-FE-Insulator-Metal (MFIM) and Metal-FE-Insulator-Semiconductor (MFIS) stacks. Our analysis is based on 2D phase field…

The influence of defects on electron transport in single-wall carbon nanotube field effect transistors (CNFETs) is probed by combined scanning gate microscopy (SGM) and scanning impedance microscopy (SIM). SGM reveals a localized field…

The need of high brightness micro-displays in portable applications dedicated to mixed and/or virtual reality has drawn an important research wave on InGaN/GaN based micro-sized light emitting diodes ({\mu}LEDs). We propose to use a SPICE…

A 20-band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to examine the ON-current variations to size variations of [110] oriented…

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…

High performance p- and n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) are obtained by using high and low work function metals, Pd and Al as source/drain (S/D) electrodes respectively. Ohmic contacts made to…

Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time; thereby removing uncertainties in calculated mobility…

Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive…

In this paper, we study the vulnerability of 5nm node FinFET and nanowire (20nm gate length) and their corresponding SRAM under radiation. Ab initio tools, SRIM, PHITS, and GEANT4, are used to find the Linear Energy Transfer (LET) of…

Boltzmann tyranny poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative…

Carbon Nanotube (CNT) appears as a promising candidate to shrink field-effect transistors (FET) to the nanometer scale. Extensive experimental works have been performed recently to develop the appropriate technology and to explore DC…

Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for…

Short channel (~80 nm) n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) with potassium (K) doped source and drain regions and high-k gate dielectrics (ALD HfO2) are obtained. For nanotubes with diameter ~ 1.6 nm…

Electronic devices that work in the quantum regime often employ hybrid nanostructures to bring about a nonlinear behaviour. The nonlinearity that these can provide has proven to be useful, in particular, for applications in quantum…

In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an…

The use of carbon nanotube (CNT) field-effect transistors (FETs) in microwave circuit design requires an appropriate, immediate and efficient description of their performance. This work describes a technique to extract the parameters of an…

A new DC thermal model of Carbon Nanotube Field Effect Transistors (CNTFETs) is proposed. The model is based on a number of fitting parameters depending on bias conditions by third order polynomials. The model includes three thermal…

Compute-in-memory (CiM) is a promising approach to alleviating the memory wall problem for domain-specific applications. Compared to current-domain CiM solutions, charge-domain CiM shows the opportunity for higher energy efficiency and…

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off…