相关论文: Negative capacitance overcomes Schottky-gate limit…
In this paper, the Ni Schottky barrier on GaN epilayer grown on free standing substrates has been characterized. First, transmission electrical microscopy (TEM) images and nanoscale electrical analysis by conductive atomic force microscopy…
Ambipolar currents in Germanium p-type nanowire Schottky barrier MOSFETs were calculated fully quantum-mechanically by using the multi-band k.p method and the non-equilibrium Green's function approach. We investigated the performance of…
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…
We report over 3 kV breakdown voltage and ultra-low leakage (011) \b{eta}-Ga2O3 power devices utilizing Schottky barrier engineering and high-permittivity (\k{appa}) dielectric (ZrO2) field plate. The (011) orientation of \b{eta}-Ga2O3…
Recently demonstrated metal-semiconductor heterojunctions with few-atom thickness show their promise as 2D Schottky contacts for future integrated circuits and nanoelectronics. The theory for 3D Schottky contacts, however, fails on these…
Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of…
Atomically thin MoS2 has recently emerged as a very attractive material for nanoscale optoelectronic devices. While n-type transport in MoS2 devices has been demonstrated, hole conduction has been more challenging. Here we show…
Contact resistance is a severe performance bottleneck for electronic devices based on two-dimensional layered (2D) semiconductors, whose contacts are Schottky rather than Ohmic. Although there is general consensus that the injection…
For the first time, n-type few-layer MoS2 field-effect transistors with graphene/Ti as the hetero-contacts have been fabricated, showing more than 160 mA/mm drain current at 1 {\mu}m gate length with an on-off current ratio of 107. The…
This work explores the consequences of introducing a piezoelectric gate barrier in a normal field-effect transistor. Because of the positive feedback of strain and piezoelectric charge, internal charge amplification occurs in such an…
Taking into account the available experimental results, we model the electronic properties and current-voltage characteristics of a ferromagnet-semiconductor junction. The Fe/GaAs interface is considered as a Fe/(i-GaAs)/n+-GaAs/n-GaAs…
We fabricate planar all-graphene field-effect transistors with self-aligned side-gates at 100 nm from the main graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1V with conductance modulation of…
As transistor footprint scales down to sub-10 nm regime, the process development for advancing to further technology nodes has encountered slowdowns. Achieving greater functionality within a single chip requires concurrent development at…
Rapid electron transport in the quantum well triggers many novel physical phenomena and becomes a critical point for the high-speed electronics. Here, we found electrical properties of the titanium oxide changed from semiconducting to…
In this work, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-GaN gate HEMTs, which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/…
We report the fabrication of back-gated field-effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes. The MoSe2 FETs are n-type and possess a high gate modulation, with On/Off ratios larger than 106. The devices…
A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-state related gate lag. Two high-density two-dimensional electron gas (2DEG)…
A low Schottky barrier height (SBH) at source/drain contact is essential for achieving high drive current in atomic layer MoS2 channel based field-effect transistors. Approaches such as choosing metals with appropriate work functions and…
We report a dramatic current reduction, or a resistance increase, by a few orders of magnitude of two common-anode Au/Ti/pGaN Schottky junctions annealed within a certain annealing condition window (600 - 700 oC, 1 - 4 min). Results from…
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire…