基于65 nm CMOS工艺实现的类比像素测试结构时间性能研究
仪器与探测器
2025-01-09 v2
摘要
在CERN EP研发的单晶体管阵列传感器项目中，Tower Partners Semiconductor Co（TPSCo）65 nm工艺已获认证并用于ALICE ITS3升级项目。设计了一种含快速像素级运算放大器缓冲器的类比像素测试结构（APTS），用于小型4×4像素矩阵，搭载带小收集电极和高度非均匀电场的传感器，以实现对该工艺下像素性能的详尽表征。对多种像素设计方案的芯片进行了120 GeV/c正硫化物束的测试。结果表明，性能最佳的APTS-OA原型方案实现了63 ps的时间分辨率，检测效率超99%，空间分辨率达2 μm，凸显TPSCo 65 nm CMOS成像技术在高能物理及其他需精确计时、高检测效率和优异空间分辨率的领域的潜力。
引用
@article{arxiv.2407.18528,
title = {Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process},
author = {Gianluca Aglieri Rinella and Luca Aglietta and Matias Antonelli and Francesco Barile and Franco Benotto and Stefania Maria Beolè and Elena Botta and Giuseppe Eugenio Bruno and Francesca Carnesecchi and Domenico Colella and Angelo Colelli and Giacomo Contin and Giuseppe De Robertis and Florina Dumitrache and Domenico Elia and Chiara Ferrero and Martin Fransen and Alex Kluge and Shyam Kumar and Corentin Lemoine and Francesco Licciulli and Bong-Hwi Lim and Flavio Loddo and Magnus Mager and Davide Marras and Paolo Martinengo and Cosimo Pastore and Rajendra Nath Patra and Stefania Perciballi and Francesco Piro and Francesco Prino and Luciano Ramello and Arianna Grisel Torres Ramos and Felix Reidt and Roberto Russo and Valerio Sarritzu and Umberto Savino and David Schledewitz and Mariia Selina and Serhiy Senyukov and Mario Sitta and Walter Snoeys and Jory Sonneveld and Miljenko Suljic and Triloki Triloki and Andrea Turcato},
journal= {arXiv preprint arXiv:2407.18528},
year = {2025}
}