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This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and…

Josephson junction transistors and 50-junction arrays with linear junction dimensions from 200 nm down to 70 nm were fabricated from standard Nb/AlOx/Nb trilayers. The fabrication process includes electron beam lithography, dry etching,…

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance…

We report on transport measurement study of top-gated field effect transistors made out of InSb nanowires grown by chemical vapor deposition. The transistors exhibit ambipolar transport characteristics revealed by three distinguished…

In this paper a low power multiplier is proposed. The proposed multiplier utilizes Broken-Array Multiplier approximation method on the conventional modified Booth multiplier. This method reduces the total power consumption of multiplier up…

We report record performance for black phosphorus p-MOSFETs. The devices have locally patterned back gates and 20-nm-thick HfO2 gate dielectrics. Devices with effective gate length, Leff = 1.0 um display extrinsic transconductance, gm, of…

Single-electron transistors have been proposed to be used as a read-out device for Cooper pair charge qubits. Here we show that a coupled superconducting transistor at a threshold voltage is much more effective in measuring the state of a…

Conventional readout of a superconducting nanowire single-photon detector (SNSPD) sets an upper bound on the output voltage to be the product of the bias current and the load impedance, $I_\mathrm{B}\times Z_\mathrm{load}$, where…

We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a…

The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot…

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate…

Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address the density and volatility issues, but have been limited by…

AlN has the largest bandgap in the wurtzite III-nitride semiconductor family, making it an ideal barrier for a thin GaN channel to achieve strong carrier confinement in field-effect transistors, analogous to silicon-on-insulator technology.…

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire…

We demonstrate a 12 quantum dot device fabricated on an undoped Si/SiGe heterostructure as a proof-of-concept for a scalable, linear gate architecture for semiconductor quantum dots. The device consists of 9 quantum dots in a linear array…

More than 3 kV breakdown voltage was demonstrated in monolithic bidirectional GaN HEMTs for the first time having potential applications in 1200V or 1700V-class novel power converters. The on resistance of the fabricated transistors was ~20…

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…

Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial…

Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to conventional deep neural networks at a fraction of the cost in terms of memory and energy. In this paper, we introduce the XNOR Neural Engine (XNE), a fully…

We consider general multi-antenna fading channels with coarsely quantized outputs, where the channel is unknown to the transmitter and receiver. This analysis is of interest in the context of sensor network communication where low power and…