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We demonstrate a 36$\times$36 gate electrode crossbar that supports 648 narrow-channel field effect transistors (FET) for gate-defined quantum dots, with a quadratic increase in quantum dot count upon a linear increase in control lines. The…

This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This…

A low-noise amplifier (LNA) amplifies a very low-power signal without significantly degrading its signal-to-noise ratio. This paper provides the design of a linear low noise amplifier with the transistor BFP 640 using bilateral approach…

The need for a high-performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize the latest technique identified as oversampling systems. It was the most economical modulator and decimation in…

Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the…

Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detection technology that can, in principle, provide significantly greater responsivity and improved noise performance than traditional charge coupled device (CCD)…

Achieving high crystalline quality Ge$_{1-x}$Sn$_{x}$ semiconductors at Sn content exceeding 10\% is quintessential to implementing the long sought-after silicon-compatible mid-infrared photonics. Herein, by using sub-20 nm Ge nanowires as…

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…

Although the measurement of current is now defined with respect to the electronic charge, producing a current standard based on a single-electron source remains challenging. The error rate of a source must be below 0.01 ppm, and many such…

Here we present the first demonstration and in-depth study of unreleased acoustic resonators in 14nm FinFET technology in the IEEE X band, which offer a zero-barrier-to-entry solution for high Q, small footprint, resonant tanks integrated…

Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the…

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation…

In this article, we propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene…

A four-stage operational transconductance amplifier (OTA) for ultra-low-power applications is introduced in this paper. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the…

Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized…

The possibility of optimization of high voltage hybrid SIT-MOS transistors (HSMT) by local reduction of the lifetime near anode emitter and/or reduction of the anode emitter injection ability by three different ways has been investigated…

We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the…

Mixed-signal hardware accelerators for deep learning achieve orders of magnitude better power efficiency than their digital counterparts. In the ultra-low power consumption regime, limited signal precision inherent to analog computation…

Single electron transistors (SETs) are fabricated by placing single walled carbon nanotubes (SWNTs) on a 100 nm wide local Al/Al2O3 bottom gate and then contacting with Pd electrodes. Coulomb oscillations up to 125 K were observed and…

The operation of an integrated two-dimensional complementary metal-oxide-semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET…