Related papers: Single bit full adder design using 8 transistors w…
This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired…
The minimum average signal-to-noise ratio (SNR) per bit required for error-free transmission over a fading channel is derived, and is shown to be equal to that of the additive white Gaussian noise (AWGN) channel, which is $-1.6$ dB.…
We introduce a new output amplifier for fully-depleted thick p-channel CCDs based on double-gate MOSFETs. The charge amplifier is an n-type MOSFET specifically designed and operated to couple the fully-depleted CCD with high charge-transfer…
We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a…
We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection…
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND and OR gates. The proposed AND gate…
This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. By integrating a…
We propose and demonstrate experimentally a novel design of single-electron quantum dots. The structure consists of a narrow band gap quantum well that can undergo a transition from the hole accumulation regime to the electron inversion…
A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 $\mu$m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no…
This work presents a fully discrete, low cost digital isolator requiring no specialized ICs and implemented entirely with general purpose transistors and a two layer PCB embedded air core transformer. The design avoids vendor lock in and…
An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a…
Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With dual-sided power rails and signal tracks, FFET can achieve…
On-silicon inductors using a bulk 0.18 {\mu}m CMOS process have been designed. By shunting different metal layers in parallel, inductor values and quality factors were simulated. Selected inductors were then employed in two open-loop buck…
Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature.…
The ability to maximize the performance during peak workload hours and minimize the power consumption during off-peak time plays a significant role in the energy-efficient systems. Our previous work has proposed a high-performance…
Guided by a comprehensive analysis of accumulation mode transistor physics and oxide semiconductor materials properties, we demonstrate an innovative oxide semiconductor transistor structure and process flow that break the constraint…
In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not…
A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF…
In this letter, fin-shape tri-gate $\beta$-Ga$_{2}$O$_{3}$ lateral MESFETs are demonstrated with a high power figure of merit of 0.95 GW/cm$^{2}$ - a record high for any $\beta$-Ga$_{2}$O$_{3}$ transistor to date. A low-temperature undoped…
The requirements and details of designing a measuring cell and low-back-action deeply-cooled amplifier for quantum measurements at 10 mK are discussed. This equipment is a part of a microwave single-photon counter based on a superconducting…