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We report a robust process for fabrication of surface-gated Si/SiGe quantum dots (QDs) with an integrated superconducting single-electron transistor (S-SET) charge sensor. A combination of a deep mesa etch and AlOx backfill is used to…
To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced. This paper presents the first (to the best of…
This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for…
Ambipolar dual-gate transistors based on two-dimensional (2D) materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with suppressed…
We discuss how a single Cooper-pair transistor may be used to detect the superconducting phase difference by using the phase dependence of the input capacitance from gate to the ground. The proposed device has a low power dissipation…
The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a…
Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted…
An array of DEPFET pixels is one of several concepts to implement an active pixel sensor. Similar to PNCCD and SDD detectors, the typically 0.45 mm thick silicon sensor is fully depleted by the principle of sideward depletion. They have…
Achieving high performance, energy efficiency, and cost-effectiveness while maintaining architectural flexibility is a critical challenge in the development and deployment of edge AI devices. Monolithic SoC designs struggle with this…
CMOS imagers are becoming increasingly popular in astronomy. A very low noise level is required to observe extremely faint targets and to get high-precision flux measurements. Although CMOS technology offers many advantages over CCDs, a…
The lower conduction power losses and the positive temperature coefficient that favours parallel connections, make Silicon Carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) to be an excellent replacement of existing…
Enabling applications for solid state quantum technology will require systematically reducing noise, particularly dissipation, in these systems. Yet, when multiple decay channels are present in a system with similar weight, resolution to…
The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted…
A well-balanced detector with high sensitivity and low noise is presented in this paper. The two-stage amplification structure is used to increase electronic gain while keeping an effective bandwidth of about 70 MHz. In order to further…
Non-volatile memories (NVMs) offer negligible leakage power consumption, high integration density, and data retention, but their non-volatility also raises the risk of data exposure. Conventional encryption techniques such as the Advanced…
This study unveils a comprehensive design strategy, intricately addressing the realization of transmon qubits, the design of Josephson parametric amplifiers, and the development of an innovative fully integrated receiver dedicated to…
Graphene nanoribbon (GNR) emerges as an exceptionally promising channel candidate due to its tunable sizable bandgap (0-3 eV), ultrahigh carrier mobility (up to 4600 cm^(2) V^(-1) s^(-1)), and excellent device performance (current on-off…
Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…
The ubiquitous use of sensing and signal processing is increasing exponentially with the advance of the Internet of Everything (IoE). In this context, the design of every time more power efficient sensor nodes is a must. Within these nodes,…
This paper introduces a new, highly energy-efficient, Adiabatic Capacitive Neuron (ACN) hardware implementation of an Artificial Neuron (AN) with improved functionality, accuracy, robustness and scalability over previous work. The paper…