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This paper presents a low power, low cost transceiver architecture to implement radar-on-a-chip. The transceiver comprises of a full ultra-wideband (UWB) transmitter and a full UWB band receiver. A design methodology to maximize the tuning…
Scaling of GaN high-electron-mobility transistors (HEMTs) usually increases gate leakage current and deteriorates breakdown characteristic, limiting the maximum drain current and output power density. These bottlenecks can be circumvented…
It is shown that the noise-limited charge sensitivity of a single-electron transistor using superconductors (of either $SISIS$ or $NISIN$ type) operating near the threshold of quasiparticle tunneling, can be considerably higher than that of…
The large attention-based encoder-decoder network (Transformer) has become prevailing recently due to its effectiveness. But the high computation complexity of its decoder raises the inefficiency issue. By examining the mathematic…
Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of…
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic…
This paper presents the analysis, design, fabrication, and measurement of an integrated low-noise amplifier (LNA) implemented using a 130 nm CMOS technology, operating in the 2.4 GHz band. The LNA is a crucial component in the performance…
The radiation response of a 0.25 um silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. Device-level characterization showed threshold voltage change…
- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage…
A robust square wave generator employing a sole capacitor and two resistors has been presented in this study. Low power and popular translinear circuit scheme of Second generation current controlled current conveyor-CCCII has been taken as…
We propose a joint TDC and multi-time-gated imaging single-photon avalanche diode LiDAR sensor featuring a maximum detection range of 108m with a minimum depth resolution (least significant bit) of 2.93mm, fabricated in 110nm CMOS…
State of the Art Wireless Power Transfer (WPT) systems, based on conventional copper coils, are known to exhibit efficiencies well above 90% when operated in the resonantly coupled mid-range regime. Besides full system efficiency, the area-…
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3…
Now a day reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic from…
An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and…
The realization of all-optical integration and optical computing has always been our goal. One of the most significant challenges is to make integrated all-optical logic devices as small as possible. Here, we report the implementation of…
The transmon, which has a short gate time and remarkable scalability, is the most commonly utilized superconducting qubit, based on the Cooper pair box as a qubit or coupler in superconducting quantum computers. Lattice and heavy-hexagon…
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…
Modern communication receiver architectures center around digital signal processing (DSP), with the bulk of the receiver processing being performed on digital signals obtained after analog-to-digital conversion (ADC). In this paper, we…
Researchers and designers are facing problems with memory and power walls, considering the pervasiveness of Von-Neumann architecture in the design of processors and the problems caused by reducing the dimensions of deep sub-micron…