Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of indium phosphide (InP) NW than silicon NW makes it particularly well-suited for high-performance (HP) electronics applications. In this work, we perform an ab initio quantum transport simulation to investigate the performance limit of sub-5-nm gate length (Lg) GAA InP NW FETs. The GAA InP NW FETs with Lg of 4 nm can meet the International Technology Roadmap for Semiconductors (ITRS) requirements for HP devices from the perspective of on-state current, delay time, and power dissipation. We also investigate the impact of strain on 3-nm-Lg GAA InP NW FETs. The application of tensile strain results in a remarkable increase of over 60% in the on-state current. These results highlight the potential of GAA InP NW FETs for HP applications in the sub-5-nm Lg region.
@article{arxiv.2308.14045,
title = {Sub-5 nm Gate-All-Around InP Nanowire Transistors Towards High-Performance Devices},
author = {Linqiang Xu and Lianqiang Xu and Qiuhui Li and Shibo Fang and Ying Li and Ying Guo and Aili Wang and Ruge Quhe and Yee Sin Ang and Jing Lu},
journal= {arXiv preprint arXiv:2308.14045},
year = {2023}
}