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The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET…

The paper presents simulation study of thin ferroelectrics (Si doped HfO2, PZT) PGP FDSOI NCFETs at circuit level for high performance, low VDD low-power digital circuits. The baseline PGP FDSOI MOSFET has 20 nm metal gate length with…

Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI…

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…

The standard technique to electrically isolate the $n^+$ implants of segmented silicon sensors fabricated on high-ohmic $p$-type silicon are $p^+$-implants. Although the knowledge of the $p^+$-implant dose and of the doping profile is…

Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO2, Si3N4, or crystalline-Si…

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by…

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed…

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI…

Controlled atomic scale fabrication of functional devices is one of the holy grails of nanotechnology. The most promising class of techniques that enable deterministic nanodevice fabrication are based on scanning probe patterning or surface…

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our…

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has…

A novel method for doping plasmas in pulsed-power experiments with gaseous elements has been developed. A fast gas valve, a nozzle, and a skimmer are used to generate an ultrasonic gas beam that is injected into a planar-geometry…

We propose a novel Forked-Contacts, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation…

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge0.96Sn0.04 nanowire MOSFETs (NWFETs) were simulated using rigorous ballistic quantum…

In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution…

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the…

As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…

This letter reports on the design and demonstration of high-performance Beta-Ga2O3 FinFETs utilizing MOCVD-grown Si delta-doped channels to achieve enhanced carrier transport and electrostatic control. A record high sheet charge density of…

Local density calculations of the electronic structure of FeSi, FeSi_{1-x}Al_x and Fe_{1-x}Ir_xSi systems in the B20 structure are presented. Pure FeSi has a semi-conducting gap of 6 mRy at 0 K. Effects of temperature (T) in terms of…