相关论文: Developments Toward a 250-nm, Fully Planarized Fab…

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted…

Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs. We have been developing a ten-superconductor-layer…

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging…

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias,…

A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated…

To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized…

Josephson junction transistors and 50-junction arrays with linear junction dimensions from 200 nm down to 70 nm were fabricated from standard Nb/AlOx/Nb trilayers. The fabrication process includes electron beam lithography, dry etching,…

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on…

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized…

We have developed a fabrication technology for the development of large-scale superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels uses four metal layers including 3 Nb…

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional…

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same…

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of…

We present a new process for fabricating vertical NbN-MgO-NbN Josephson junctions using self-aligned silicon nitride spacers. It allows for a wide range of junction areas from 0.02 um^2 to several 100 um^2. At the same time, it is suited…

A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10…

We have developed a novel fabrication process for ultra-small, full-epitaxial NbN Josephson junctions on a silicon (Si) substrate. A full-epitaxial NbN/AlN/NbN tri-layer was grown on a Si (100) wafer with a (200)-oriented TiN buffer layer.…

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ…

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process,…

We report the realization of multilayer three-dimensional nanobridge Josephson junctions based on Nb/NbN and Nb/TiN superconducting stacks fabricated using electron-beam lithography and chlorine-based dry etching. In this architecture, a…

We characterize inductors fabricated from ultra-thin, approximately 100 nm wide strips of niobium (Nb) and niobium nitride (NbN). These nanowires have a large kinetic inductance in the superconducting state. The kinetic inductance scales…