相关论文: Compact Modeling of 0.35 micron SOI CMOS Technolog…

Scalable solid-state quantum computers will require integration with analog and digital electronics. Efficiently simulating the quantum-classical electronic interface is hence of paramount importance. Here, we present Verilog-A compact…

This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs…

Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…

Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential…

The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic, yet computationally efficient, empirical models that can capture all observed…

Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…

We have presented a compact MOSFET model, which allows us to describe the I-V characteristics of irradiated long-channel and short-channel transistors in all operation modes at different measurement temperatures and interface trap…

This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms…

The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although…

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on…

Transistors are the basic building blocks for all electronics. Accurate prediction of their current-voltage (IV) characteristics enables circuit simulations before the expensive silicon tape-out. In this work, we propose using deep neural…

We present a physics-based compact model for two-dimensional (2D) field-effect transistors (FETs) based on monolayer semiconductors such as MoS2. A semi-classical transport approach is appropriate for the 2D channel, enabling simplified…

The experiment of the future electron-positron colliders has unprecedented requirements on the vertex resolution, such as around 3micron single point resolution for the inner most detector layer, with fast readout, and very low…

The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various…

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an…

A monolithic pixel sensor in deep-submicron Silicon-On-Insulator (SOI) CMOS technology has been designed, manufactured and characterised. This technology is of significant interest for applications in particle tracking and imaging. The…

This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a…

We present a modeling approach based on the BSIM-IMG compact model to capture the deep-cryogenic behavior of MOSFET devices in a 22-nm FDSOI technology. The modeling flow is based on DC measurements to extract static parameters including…

1/f noise is a critical figure of merit for the performance of transistors and circuits. For two-dimensional devices (2D-FETs), and especially for applications in the GHz range where short-channel FETs are required, velocity saturation (VS)…

In this work we introduce a compact model for mushroom-type phase-change memory devices that incorporates the shape and size of the amorphous mark under different programming conditions, and is applicable to both projecting and…