相关论文: Designing power efficient transistors using narrow…

Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the…

Two-dimensional (2D) semiconductors have attracted tremendous interests as natural passivation and atomically thin channels that could facilitate continued transistor scaling. However, air-stable 2D semiconductors with high performance were…

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved…

As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…

Chemical vapor deposition has been most recently employed to fabricate centimeter-scale high-quality single-layer MoSi2N4 (Science; 2020;369; 670). Motivated by this exciting experimental advance, herein we conduct extensive…

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used.…

Scaling transistors' dimensions has been the thrust for the semiconductor industry in the last 4 decades. However, scaling channel lengths beyond 10 nm has become exceptionally challenging due to the direct tunneling between source and…

Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with…

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer…

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating…

Experimental realization of single-layer MoSi2N4 is among the latest groundbreaking advances in the field of two-dimensional (2D) materials. Inspired by this accomplishment, herein we conduct first-principles calculations to explore the…

Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor…

The recent synthesis of MoSi2N4 material, along with theoretical predictions encompassing the entire family of chemical analogs, has opened up a new array of low-dimensional materials for a diverse range of optoelectronics and photovoltaics…

The electronic properties of a field-effect transistor with two different structures of MoSi$_2$N$_4$ and WSi$_2$N$_4$ monolayers as the channel material in the presence of biaxial strain are investigated. The band structures show that…

We propose and investigate the intrinsically thinnest transistor concept: a monolayer ballistic heterojunction bipolar transistor based on a lateral heterostructure of transition metal dichalcogenides. The device is intrinsically thinner…

While 2D materials have enormous potential for future device technologies, many challenges must be overcome before they can be deployed at an industrial scale. One of these challenges is identifying the right semiconductor/insulator…

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…

Two-dimensional ferroelectric materials are beneficial for power-efficient memory devices and transistor applications. Here, we predict out-of-plane ferroelectricity in a new family of buckled metal oxide (MO; M: Ge, Sn, Pb) monolayers with…

Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors…

With the miniaturization and integration of nanoelectronic devices, efficient heat removal becomes a key factor affecting the reliable operation of the nanoelectronic device. With the high intrinsic thermal conductivity, good mechanical…