相关论文: InAs nanowire transistors with multiple, independe…
Semiconductor nanowires can be utilized to create quantum dot qubits. The formation of quantum dots is typically achieved by means of bottom gates created by a lift-off process. As an alternative, we fabricated flat buried bottom gate…
The combination of core/shell geometry and band gap engineering in nanowire heterostructures can be employed to realize systems with novel transport and optical properties. Here, we report on the growth of InAs/InP/GaAsSb core-dual-shell…
A central challenge in developing practical quantum processors is maintaining low control complexity while scaling to large numbers of qubits. Trapped-ion systems excel in small-scale operations and support rapid qubit scaling via…
Magnonics is a rapidly growing field, attracting much attention for its potential applications in data transport and processing. Many individual magnonic devices have been proposed and realized in laboratories. However, an integrated…
We present a comprehensive electrical characterization of an InAs/InP nanowire heterostructure, comprising two InP barriers forming a quantum dot (QD), two adjacent lead segments (LSs) and two metallic contacts, and demonstrate how to…
We present a novel technique for the manipulation of the energy spectrum of hard-wall InAs/InP nanowire quantum dots. By using two local gate electrodes, we induce a strong electric dipole moment on the dot and demonstrate the controlled…
Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are…
Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene,…
A detailed numerical analysis of the magnetization reversal processes in multisegmented nanowire arrays was developed. The nanowires have a long aspect ratio and are formed by magnetic and non-magnetic sections alternately arranged in such…
We report on the growth of axial InAs-on-GaAs nanowire heterostructures on silicon by molecular beam epitaxy using 20 nm diameter Au catalysts. First, the growth parameters of the GaAs nanowire segment were optimized to achieve a pure…
Rapid and reproducible assembly of aligned nanostructures on a wafer-scale is a crucial, yet one of the most challenging tasks in the incorporation of nanowires into integrated circuits. We present the synthesis of a periodic nanochannel…
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic…
We demonstrate that semiconductor nanowires measuring just a few nanometers in diameter can be translated, rotated, cut, fused and organized into nontrivial structures using holographic optical traps. The holographic approach to…
Here, we demonstrate an approach that provides a precise control of the dimension of InAs from one-dimensional nanowires to wafer-scale free-standing two-dimensional nanosheets, which have a high degree of crystallinity and outstanding…
We report the detection of a gate-tunable kinetic inductance in a hybrid InAs/Al nanowire. For this purpose, we have embedded the nanowire into a quarter-wave coplanar waveguide resonator and measured the resonance frequency of the circuit.…
We have fabricated and measured ballistic graphene transistors with two oblique gates that can be independently biased. The gate lengths are about 38 nm and are separated by a distance of 30 nm, the tilting angle being of 45o with respect…
Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved…
The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a…
Realization of a robust nanotube-heterostructure tunneling transistors [Solid State Comm. 116, p. 569 (2000)] requires the difficult formation [Science 293, p. 76 (2001)] of a central nanoscale barrier separating a pair of outside metallic…
A wide family of two dimensional (2D) systems, including stripe-phase superconductors, sliding Luttinger liquids, and anisotropic 2D materials, can be modeled by an array of coupled one-dimensional (1D) electron channels or nanowire arrays.…