相关论文: Optimum High-k Oxide for the Best Performance of U…

We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…

Since the 1960's when Gordon Moore proposed that the transistor density in our electronic devices should double every two years while the cost is halved, the semiconductor industry has taken this statement to heart. Over the last few…

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating…

Two-dimensional (2D) layered materials-based field-effect transistors (FETs) are promising for ultimate scaled electron device applications because of the improved electrostatics to atomically thin body thickness. However, compared with the…

As the continuing down-scaling of field-effect transistors (FETs) in more-than-Moore integrated circuits, finding new functional two-dimensional (2D) materials with a higher dielectric constant (high-k) serve as gate dielectrics is…

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL…

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO$_2$ and HfO$_2$ is derived. The model…

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon…

Two-dimensional (2D) layered materials are promising for replacing Si to overcome the scaling limit of recent ~5 nm-length metal-oxide-semiconductor field-effect transistors (MOSFETs). However, the insulator/2D channel interface severely…

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform…

Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable…

Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron…

Advanced logic transistors require gate dielectrics that achieve sub-nanometer equivalent oxide thickness (EOT), suppress leakage, and satisfy three key requirements: (i) compatibility with RMG-like high-temperature processing, (ii)…

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…

We report Beta-AlGaO/Ga2O3 tri-gate heterostructure MOSHEMTs incorporating a thin 5 nm Al2O3 gate oxide layer for improved gate control and reduced leakage. The devices were fabricated on AlGaO/GaO heterostructures grown by ozone MBE on…

We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a…

Because high electron mobility transistors (HEMTs) often exhibit significant gate leakage during high-temperature operation, the choice of Schottky metal is critical. Increased gate leakage and reduced ON/OFF ratio are unsuitable for the…

Field-effect transistors (FETs) with single gates are adversely affected by short channel effects such as drain-induced barrier lowering (DIBL) and increases in the magnitude of sub-threshold swing as the channel length is reduced.…

Two-dimensional (2D) semiconductors have been suggested both for ultimately-scaled field-effect transistors (FETs) and More-than-Moore nanoelectronics. However, these targets can not be reached without accompanying gate insulators which are…

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for…