相关论文: Underlap Optimization in HFinFET in Presence of In…

We report the fabrication and study of Hall bar MOSFET devices in which an overlapping-gate architecture allows four-terminal measurements of low-density 2D electron systems, while maintaining a high density at the ohmic contacts.…

We report record performance for black phosphorus p-MOSFETs. The devices have locally patterned back gates and 20-nm-thick HfO2 gate dielectrics. Devices with effective gate length, Leff = 1.0 um display extrinsic transconductance, gm, of…

In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in particular, that of an inner loop. We describe a control-flow…

Hybrid transceiver can strike a balance between complexity and performance of multiple-input multiple-output (MIMO) systems. In this paper, we develop a unified framework on hybrid MIMO transceiver design using matrix-monotonic…

The possibility of optimization of high voltage hybrid SIT-MOS transistors (HSMT) by local reduction of the lifetime near anode emitter and/or reduction of the anode emitter injection ability by three different ways has been investigated…

The performance limits of the multilayer graphene nanoribbon (GNR) field-effect transistor (FET) are assessed and compared to those of monolayer GNR FET and carbon nanotube (CNT) FET. The results show that with a thin high-k gate insulator…

Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation…

Surface dielectric loss of superconducting transmon qubit is believed as one of the dominant sources of decoherence. Reducing surface dielectric loss of superconducting qubit is known to be a great challenge for achieving high quality…

We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in…

This work presents a combined analytical and simulation-based study of a 3D-integrated quantum chip architecture. We model a flip-chip-inspired structure by stacking two superconducting qubits fabricated on separate high-resistivity silicon…

Hypergraphs provide a natural representation for many-to-many relationships in data-intensive applications, yet their scalability is often hindered by high memory consumption. While prior work has improved computational efficiency, reducing…

Massively pre-trained transformer models are computationally expensive to fine-tune, slow for inference, and have large storage requirements. Recent approaches tackle these shortcomings by training smaller models, dynamically reducing the…

Robust transceiver design against unresolvable system uncertainties is of crucial importance for reliable communication. For instance, full-duplex communication suffers from such uncertainties when canceling the self-interference, since…

Inductively shunted superconducting qubits, such as the unimon qubit, combine high anharmonicity with protection from low-frequency charge noise, positioning them as promising candidates for the implementation of fault-tolerant…

High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that…

Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of…

Vision Transformers require significant computational resources and memory bandwidth, severely limiting their deployment on edge devices. While recent structured pruning methods successfully reduce theoretical FLOPs, they typically operate…

Generative models have achieved remarkable success across various applications, driving the demand for multi-GPU computing. Inter-GPU communication becomes a bottleneck in multi-GPU computing systems, particularly on consumer-grade GPUs. By…

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…

Compressing word embeddings is important for deploying NLP models in memory-constrained settings. However, understanding what makes compressed embeddings perform well on downstream tasks is challenging---existing measures of compression…