相关论文: Area-Efficient Selective Multi-Threshold CMOS Desi…

The performance of spatial multiplexing systems with linear minimum-mean-squared-error receivers is investigated in ad hoc networks. It is shown that single-stream transmission is preferable over multi-stream transmission, due to the weaker…

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is…

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on…

This paper focuses on robust transceiver design for throughput enhancement on the interference channel (IC), under imperfect channel state information (CSI). In this paper, two algorithms are proposed to improve the throughput of the…

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM…

Machine-type communication (MTC) is the key technology to support data transfer among devices (sensors and actuators). Cellular communication technologies are developed mainly for "human-type" communications, while enabling MTC with…

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets…

In this paper, we investigate a multiuser relay system with simultaneous wireless information and power transfer. Assuming that both base station (BS) and relay station (RS) are equipped with multiple antennas, this work studies the joint…

In this paper, we examine the outage performance of a cognitive relay network, which is comprised of a secondary transmitter (ST), multiple decode-and-forward (DF) relays and a secondary destination (SD). We propose a multi-relay selection…

Phase Coded (PC) waveforms possess desirable Auto-Correlation Function (ACF) properties for use in radar and sonar systems. However, their spectra possess high spectral leakage due to the abrupt phase transitions between the chips in the…

This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories…

Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as…

In this paper, we consider the downlink of a massive multiple-input-multiple-output (MIMO) single user transmission system operating in the millimeter wave outdoor narrowband channel environment. We propose a novel receive spatial…

This paper critically examines the leakage current reduction techniques for improving the performance of poly-Si TFTs used in active matrix liquid crystal displays. This is a first comprehensive study in literature on this topic. The review…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache…

This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This…

This paper presents a novel framework for optimizing capacitor selection in electronic design using multi-objective linear and non-linear constrained optimization techniques. We demonstrate the effectiveness of this approach in minimizing…

CMOS-transistors circuits have been used as a conventional approach for designing an analog multiplier in modern era of industrial electronics. However, previous studies have shown, that based on the working region of transistors, such as…

A non-volatile SRAM cell is proposed for low power applications using Spin Transfer Torque-Magnetic Tunnel Junction (STT-MTJ) devices. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be switched off…