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Elliptic curve cryptography (ECC) has emerged as the dominant public-key protocol, with NIST standardizing parameters for binary field GF(2^m) ECC systems. This work presents a hardware implementation of a Hybrid Multiplication technique…

密码学与安全 · 计算机科学 2025-06-25 Ruby Kumari , Gaurav Purohit , Abhijit Karmakar

Elliptic Curve Cryptography (ECC) is widely accepted for ensuring secure data exchange between resource-limited IoT devices. The National Institute of Standards and Technology (NIST) recommended implementation, such as B-163, is…

硬件体系结构 · 计算机科学 2025-06-17 Ruby Kumari , Tapas Rout , Babul Saini , Jai Gopal Pandey , Abhijit Karmakar

Cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems. Field Programmable Gate Arrays (FPGAs) having programmable logic de- vices and processing…

硬件体系结构 · 计算机科学 2014-02-20 Sruti Agarwal , Sangeet Saha , Rourab Paul , Amlan Chakrabarti

Transformer-based large language models (LLMs) rely heavily on intensive matrix multiplications for attention and feed-forward layers, with the Q, K, and V linear projections in the Multi-Head Self-Attention (MHA) module constituting a…

硬件体系结构 · 计算机科学 2025-05-22 Richie Li , Sicheng Chen

This paper presents a novel algorithm for the modulus operation for FPGA implementation. The proposed algorithm use only addition, subtraction, logical, and bit shift operations, avoiding the complexities and hardware costs associated with…

密码学与安全 · 计算机科学 2025-01-10 W. A. Susantha Wijesinghe

In modern critical infrastructure such as power grids, it is crucial to ensure security of data communications between network-connected devices while following strict latency criteria. This necessitates the use of cryptographic hardware…

密码学与安全 · 计算机科学 2025-04-08 Aniket Banerjee , Utsav Banerjee

Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with traditional FPGA platforms. However, the limited eFPGA logic and…

硬件体系结构 · 计算机科学 2025-02-13 Tousif Rahman , Gang Mao , Bob Pattison , Sidharth Maheshwari , Marcos Sartori , Adrian Wheeldon , Rishad Shafik , Alex Yakovlev

In this paper, we propose a mixed-precision convolution unit architecture which supports different integer and floating point (FP) precisions. The proposed architecture is based on low-bit inner product units and realizes higher precision…

硬件体系结构 · 计算机科学 2021-01-29 Hamzah Abdel-Aziz , Ali Shafiee , Jong Hoon Shin , Ardavan Pedram , Joseph H. Hassoun

In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive…

硬件体系结构 · 计算机科学 2011-10-20 V. Sreedeep , B. Ramkumar , Harish M Kittur

Matrix multiplication is the bedrock in Deep Learning inference application. When it comes to hardware acceleration on edge computing devices, matrix multiplication often takes up a great majority of the time. To achieve better performance…

机器学习 · 计算机科学 2021-10-12 Yuyang Zhang , Dik Hin Leung , Min Guo , Yijia Xiao , Haoyue Liu , Yunfei Li , Jiyuan Zhang , Guan Wang , Zhen Chen

Securing communication channels is especially needed in wireless environments. But applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices. If hardware is applied to realize…

密码学与安全 · 计算机科学 2011-11-09 Zoya Dyka , Peter Langendoerfer

Resource constraints in smart devices demand an efficient cryptosystem that allows for low power and memory consumption. This has led to popularity of comparatively efficient Elliptic curve cryptog-raphy (ECC). Prior to this paper, much of…

密码学与安全 · 计算机科学 2015-02-09 Yasir Malik

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a…

硬件体系结构 · 计算机科学 2025-10-27 Misaki Kida , Shimpei Sato

RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple…

应用统计 · 统计学 2016-09-21 Rourab Paul , Hemanta Dey , Amlan Chakrabarti , Ranjan Ghosh

As enterprises embrace blockchain technology, many real-world applications have been developed and deployed using permissioned blockchain platforms (access to network is controlled and given to only nodes with known identities). Such…

密码学与安全 · 计算机科学 2021-12-07 Rashmi Agrawal , Ji Yang , Haris Javaid

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators.…

信号处理 · 电气工程与系统科学 2018-06-13 Yazan Samir Algnabi , Rozita Teymourzadeh , Masuri Othman , Md Shabiul Islam

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators.…

信号处理 · 电气工程与系统科学 2018-08-09 Rozita Teymourzadeh , Yazan Samir , Masuri Othman , Mok Vee Hong

Numerical codes that require arbitrary precision floating point (APFP) numbers for their core computation are dominated by elementary arithmetic operations due to the super-linear complexity of multiplication in the number of mantissa bits.…

分布式、并行与集群计算 · 计算机科学 2022-04-14 Johannes de Fine Licht , Christopher A. Pattison , Alexandros Nikolaos Ziogas , David Simmons-Duffin , Torsten Hoefler

Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to generate the secret key that the eavesdropper has only negligible information from the identical correcting key for the communicating parties. With the…

量子物理 · 物理学 2018-09-24 Qiong Li , Bing-Ze Yan , Hao-Kun Mao , Xiao-Feng Xue

Advanced Encryption Standard (AES) implementations on Field Programmable Gate Arrays (FPGA) commonly focus on maximizing throughput at the cost of utilizing high volumes of FPGA slice logic. High resource usage limits systems' abilities to…

密码学与安全 · 计算机科学 2019-11-12 Jacob T. Grycel , Robert J. Walls
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