Matrix multiplication is the bedrock in Deep Learning inference application. When it comes to hardware acceleration on edge computing devices, matrix multiplication often takes up a great majority of the time. To achieve better performance in edge computing, we introduce a low-power Multi-layer Perceptron (MLP) accelerator based on a pipelined matrix multiplication scheme and a nonuniform quantization methodology. The implementation is running on Field-programmable Gate Array (FPGA) devices and tested its performance on handwritten digit classification and Q-learning tasks. Results show that our method can achieve better performance with fewer power consumption.
@article{arxiv.2110.04861,
title = {A Deep Learning Inference Scheme Based on Pipelined Matrix Multiplication Acceleration Design and Non-uniform Quantization},
author = {Yuyang Zhang and Dik Hin Leung and Min Guo and Yijia Xiao and Haoyue Liu and Yunfei Li and Jiyuan Zhang and Guan Wang and Zhen Chen},
journal= {arXiv preprint arXiv:2110.04861},
year = {2021}
}