相关论文: III-V Tri-Gate Quantum Well MOSFET: Quantum Ballis…
In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of…
Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors…
Extensive studies on thin films indicated a generic cubic current-voltage $I-V$ dependence as a salient feature of charge transport by tunneling. A quick glance at $I-V$ data for molecular junctions suggests a qualitatively similar…
Gate-layouts of spin qubit devices are commonly adapted from previous successful devices. As qubit numbers and the device complexity increase, modelling new device layouts and optimizing for yield and performance becomes necessary.…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…
High-quality-factor 3D cavities in superconducting circuits are ideal candidates for bosonic logical qubits as their fidelity is limited only by the low photon loss rate. However, the transmon qubits that are used to manipulate bosonic…
We report Beta-AlGaO/Ga2O3 tri-gate heterostructure MOSHEMTs incorporating a thin 5 nm Al2O3 gate oxide layer for improved gate control and reduced leakage. The devices were fabricated on AlGaO/GaO heterostructures grown by ozone MBE on…
As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor…
We introduce a silicon metal-oxide-semiconductor quantum dot architecture based on a single polysilicon gate stack. The elementary structure consists of two enhancement gates separated spatially by a gap, one gate forming a reservoir and…
Growth in the complexity and capabilities of quantum information hardware mandates access to practical techniques for performance verification that function under realistic laboratory conditions. Here we experimentally characterise the…
Quantum machine learning offers promising advantages for classification tasks, but noise, decoherence, and connectivity constraints in current devices continue to limit the efficient execution of feature map-based circuits. Gate Assessment…
Quantum gates based on geometric phases possess intrinsic noise-resilience features and therefore attract much attention. However, the implementations of previous geometric quantum computation typically require a long pulse time of gates.…
Thermally activated sub-threshold transport has been investigated in undoped triple gate MOSFETs. The evolution of the barrier height and of the active cross-section area of the channel as a function of gate voltage has been determined. The…
Decoherence of quantum states is a major hurdle towards scalable and reliable quantum computing. Lower decoherence (i.e., higher fidelity) can alleviate the error correction overhead and obviate the need for energy-intensive noise reduction…
We study one-dimensional transport in focused-ion-beam written in-plane-gate transistors on III-V heterostructures at moderately low temperatures at zero bias without any external magnetic field applied. In accordance with a recent proposal…
In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of…
A scalable spin-based quantum processor requires a suitable semiconductor heterostructure and a gate design, with multiple alternatives being investigated. Characterizing such devices experimentally is a demanding task, with the full…
We study 95 split gates of different size on a single chip using a multiplexing technique. Each split gate defines a one-dimensional channel on a modulation-doped GaAs/AlGaAs heterostructure, through which the conductance is quantized. The…
We present detailed simulations addressing recent electronic interference experiments, where a metallic gate is used to locally modify the Fermi wave-length of the charge carriers. Our numerical calculations are based on a solution of the…
The existence of the third cumulant $S_{3}$ of voltage fluctuations has demonstrated the non-Gaussian aspect of shot noise in electronic transport. Until now, measurements have been performed at low frequency, \textit{i.e.} in the classical…