相关论文: Experimental Demonstration of Single Electron Tran…

A new method to fabricate non-superconducting mesoscopic tunnel junctions by oxidation of Ti is presented. The fabrication process uses conventional electron beam lithography and shadow deposition through an organic resist mask.…

Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimizing the performances of…

We report on the fabrication and electrical characterization at millikelvin temperatures of a novel silicon single-electron transistor (Si-SET). The island and source-drain leads of the Si-SET are formed by the implantation of phosphorus…

We demonstrate a technique for creating high quality, large area tunnel junction barriers for normal-insulating- superconducting or superconducting-insulating-superconducting tunnel junctions. We use atomic layer depo- sition and an…

We tested oxidized titanium layers as barriers for hybrid Josephson junctions with high $I_cR_n$-products and for the preparation of junctions for tunneling spectroscopy. For that we firstly prepared junctions with conventional…

The fabrication of micro- and nano-scale silicon electronic devices requires precision lithography and controlled processing to ensure that the electronic properties of the device are optimized. Importantly, the Si-SiO2 interface plays a…

We have successfully fabricated micron-scale Cu-AlO$_{x} $-Al-NbN normal metal-insulator-superconductor (NIS) tunnel junction devices, using pulsed laser deposition (PLD) for NbN film growth, and electron-beam lithography and shadow…

Deep submicron Al-AlOx-Nb tunnel junctions and single electron transistors with niobium islands were fabricated by electron beam gun shadow evaporation. Using stencil masks consisting of the thermostable polymer polyethersulfone (PES) and…

We report the fabrication and characteristics of GaAs/Si p+/n+ heterojunction tunnel diodes. These diodes were fabricated via grafting the freestanding single-crystalline p-type degenerately doped GaAs (4E19 cm-3) nanomembrane (NM) onto…

Titanium silicide islands have been formed by the ultrahigh vacuum deposition of thin films of titanium (< 2 nm) on atomically clean Si(100) substrates followed by annealing to ~800 degrees C. Scanning tunneling microscopy (STM) and…

This study presents a comprehensive investigation into the exceptional superconducting attributes of titanium nitride (TiN) achieved through plasma-enhanced atomic layer deposition (PEALD) on both planar and intricate three-dimensional (3D)…

We have fabricated a variety of novel molecular tunnel junctions based on self-assembled-monolayers (SAM) of two-component solid-state mixtures of molecular wires (1,4 methane benzene-dithiol; Me-BDT with two thiol anchoring groups), and…

The discovery of a two-dimensional electron gas (2DEG) at the interface between insulating oxides has led to a well-deserved level of excitement due to possible applications as "in-plane" all-oxide nanoelectronics. Here we expand the range…

We report on a new type of single-electron transistor (SET) comprising two highly resistive Cr thin-film strips (~ 1um long) connecting a 1 um-long Al island to two Al outer electrodes. These resistors replace small-area oxide tunnel…

We have developed a fabrication process for nanoscale tunnel junctions which includes focused-ion-beam etching from different directions. By applying the process to a Nb/(Al-)Al_2O_3/Nb trilayer, we have fabricated a Nb single-electron…

We have investigated spin accumulation in Ni/Au/Ni single-electron transistors assembled by atomic force microscopy. The fabrication technique is unique in that unconventional hybrid devices can be realized with unprecedented control,…

The structure property of non-ideal Si/GaAs heterostructures that were integrated with the ultra-thin oxide (UO) tunneling interfacial layer has been systematically investigated. Si nanomembranes (NMs) were oxidized in different time…

While 2D materials have enormous potential for future device technologies, many challenges must be overcome before they can be deployed at an industrial scale. One of these challenges is identifying the right semiconductor/insulator…

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL…

This letter presents experiments on junctions fabricated by a new technique that enables the use of high quality aluminum oxide tunnel barriers with normal metal electrodes at low temperatures. Inverse proximity effect is applied to…