电路布局对单晶像素传感器中电荷收集的影响
仪器与探测器
2025-03-31 v1 高能物理 - 实验
摘要
CERN 近期开展的面向未来实验的技术研发计划中，开始调查 TPSCo 65nm ISC CMOS 成像工艺用于单晶主动像素传感器（MAPS）的技术，这类传感器适用于高能物理应用。在与 ALICE 实验及其他科研机构合作期间，多个原型器件表现出优异的性能，使该技术符合实际应用要求。与先前原型器件相同工艺制造但像素间距更大的 Hybrid-to-Monolithic（H2M）测试芯片，却呈现出意外的非对称效率模式。本文描述了一种结合 TCAD、蒙特卡罗方法和电路仿真的模拟程序，用于建模和理解这一现象。该方法成功复现了实验测量结果，并将非对称效率下降归因于由电路布局造成的低幅度势阱导致的慢速电荷收集，通过弹性违约（ballistic deficit）影响效率。
引用
@article{arxiv.2503.21853,
title = {Impact of the circuit layout on the charge collection in a monolithic pixel sensor},
author = {Corentin Lemoine and Rafael Ballabriga and Eric Buschmann and Michael Campbell and Raimon Casanova Mohr and Dominik Dannheim and Jona Dilg and Ana Dorda and Finn King and Ono Feyens and Philipp Gadow and Ingrid-Maria Gregor and Karsten Hansen and Yajun He and Lennart Huth and Iraklis Kremastiotis and Stefano Maffessanti and Larissa Mendes and Younes Otarid and Christian Reckleben and Sébastien Rettie and Manuel Alejandro del Rio Viera and Sara Ruiz Daza and Judith Schlaadt and Adriana Simancas and Walter Snoeys and Simon Spannagel and Tomas Vanat and Anastasiia Velyka and Gianpiero Vignola and Håkan Wennlöf},
journal= {arXiv preprint arXiv:2503.21853},
year = {2025}
}
备注
Presented at the Eleventh International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (Nov 18-22 2024, Strasbourg, France). Submitted to JINST