English

Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design

Materials Science 2014-05-30 v1 Mesoscale and Nanoscale Physics

Abstract

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying a control-gate voltage, which significantly increases the flexibility and versatility in digital integrated circuits.

Keywords

Cite

@article{arxiv.1405.7562,
  title  = {Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design},
  author = {Tillmann Krauss and Frank Wessely and Udo Schwalke},
  journal= {arXiv preprint arXiv:1405.7562},
  year   = {2014}
}

Comments

6 pages, 14 figures, rejected paper ESSDERC 2014

R2 v1 2026-06-22T04:26:05.243Z