In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.
@article{arxiv.1502.04181,
title = {Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications},
author = {Tillmann Krauss and Frank Wessely and Udo Schwalke},
journal= {arXiv preprint arXiv:1502.04181},
year = {2015}
}