Related papers: Negative Capacitance Enables FinFET Scaling Beyond…

The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET…

After more than 30 years of validation of Moore's law, the CMOS technology has already entered the nanoscale (sub-100nm) regime and faces strong limitations. The nanowire transistor is one candidate which has the potential to overcome the…

Nano-electronic integrated circuit technology is exclusively based on MOSFET transistor due to its scalability down to the nanometer range. On the other hand, Bipolar Junction Transistor (BJT), which provides unmatched analog…

Two-dimensional (2D) materials have great potential for use in future electronics due to their atomically thin nature which withstands short channel effects and thus enables better scalability. Device scaling is the process of reducing all…

Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones,…

This letter reports on the design and demonstration of high-performance Beta-Ga2O3 FinFETs utilizing MOCVD-grown Si delta-doped channels to achieve enhanced carrier transport and electrostatic control. A record high sheet charge density of…

Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate…

Comparators have multifarious applications in various fields, especially used in analog to digital converters. Over the years, we have seen many different designs of single stage, dynamic latch type and double tail type comparators based on…

This paper reports a comprehensive study on the impacts of temperature-change, process variation, flicker noise and device aging on the inference accuracy of pre-trained all-ferroelectric (FE) FinFET deep neural networks.…

A topological quantum field effect transistor (TQFET) uses electric field to switch a material from topological insulator ("on", with conducting edge states) to a conventional insulator ("off"), and can have low subthreshold swing due to…

FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm technology. One of the key issues to consider is, the vulnerability of FinFET based circuits to multiple node charge collection due to neutron-induced strikes. In…

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off…

Ferroelectric non-volatile capacitance-based memories enable non-destructive readout and low-power in-memory computing with 3D stacking potential. However, their limited memory window (1-10 fF/{\mu}m) requires material-device-circuit…

Desirably, the world relies on the devices being compact, as they could drive to the increased functionality of integrated circuits at the provided footstep, that is becoming more reliable. To reduce the scalability over the devices,…

In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on…

Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction TFET. The CS TFET line-tunneling current increases significantly…

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…

This paper presents a self-consistent numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characterization for a gate-all-around graded nanowire MOSFET with a high mobility axially graded…

In this work, we analyze the ferroelectric (FE) domain-wall (DW) induced negative capacitance (NC) effect in Metal-FE-Insulator-Metal (MFIM) and Metal-FE-Insulator-Semiconductor (MFIS) stacks. Our analysis is based on 2D phase field…

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled…