Related papers: Negative Capacitance Enables FinFET Scaling Beyond…

State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky barrier (SB)-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However,…

We report a method to pattern monolayer graphene nanoconstriction field effect transistors (NCFETs) with critical dimensions below 10 nm. NCFET fabrication is enabled by the use of feedback controlled electromigration (FCE) to form a…

The sensitive conductance change of semiconductor nanowires and carbon nanotubes in response to binding of charged molecules provide a novel sensing modality which is generally denoted as nanoFET sensors. In this paper, we study the scaling…

The negative capacitance (NC) stabilization of a ferroelectric (FE) material can potentially provide an alternative way to further reduce the power consumption in ultra-scaled devices and thus has been of great interest in technology and…

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20nm are examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is…

Graphene is an ideal material for fabricating atomically thin nanometre spaced electrodes. Recently, carbon-based nanoelectrodes have been employed to create single-molecule transistors and phase change memory devices. In spite of the…

Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nano-scale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we…

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved…

Advancing complementary metal-oxide-semiconductor (CMOS) technology into the sub-1-nm angstr\"om-scale technology nodes is expected to involve alternative semiconductor channel materials, as silicon transistors encounter severe performance…

Carbon nanotube field-effect transistors (CNT FETs) are regarded as promising candidates for next-generation energy-efficient computing systems. While research has employed the lift-off process to demonstrate the performance of CNT FETs,…

The dependence of random telegraph noise (RTN) amplitude on the gate overdrive in a junctionless field-effect transistor (FinFET) with rectangular and trapezoidal channel (fin) cross sections manufactured using silicon-on-insulator…

In this letter we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of a HEMT and a FinFET, to obtain excellent performance and good off state control. Followed by the description of the…

A negative capacitance has been observed in a nano-colloid between 0.1 and 10^-5 Hz. The response is linear over a broad range of conditions. The low-omega dispersions of both the resistance and capacitance are consistent with the…

This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required for their commercial uptake. The new atomic layer deposition (ALD) and conversion technique yields large area…

Integrating ferroelectric negative capacitance (NC) into the field-effect transistor (FET) promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realizing the stable static negative capacitance in…

In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution…

As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering considerable design space extension for powers, signals or even…

The relaxed and unrelaxed formation energies of neutral antisites and interstitial defects in InP are calculated using ab initio density functional theory and simple cubic supercells of up to 512 atoms. The finite size errors in the…

The electrostatic coupling between singled-walled carbon nanotube (SWNT) networks/arrays and planar gate electrodes in thin-film transistors (TFTs) is analyzed both in the quantum limit with an analytical model and in the classical limit…