This paper reviews recent progress and key challenges in process and reliability for high-performance vertical GaN transistors and diodes, focusing on the 200 mm CMOS-compatible technology. We particularly demonstrated the potential of using 200 mm diameter CTE matched substrates for vertical power transistors, and gate module optimizations for device robustness. An alternative technology path based on coalescence epitaxy of GaN-on-Silicon is also introduced, which could enable thick drift layers of very low dislocation density.
@article{arxiv.2107.02469,
title = {Vertical GaN Devices: Process and Reliability},
author = {Shuzhen You and Karen Geens and Matteo Borga and Hu Liang and Herwig Hahn and Dirk Fahle and Michael Heuken and Kalparupa Mukherjee and Carlo De Santi and Matteo Meneghini and Enrico Zanoni and Martin Berg and Peter Ramvall and Ashutosh Kumar and Mikael T. Björk and B. Jonas Ohlsson and Stefaan Decoutere},
journal= {arXiv preprint arXiv:2107.02469},
year = {2021}
}
Comments
["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][ECSEL Joint Undertaking (JU)][UltimateGaN][grant agreement No 826392]