Leakage-Aware Interconnect for On-Chip Network
硬件体系结构
2011-11-09 v1
摘要
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.
引用
@article{arxiv.0710.4731,
title = {Leakage-Aware Interconnect for On-Chip Network},
author = {Yuh-Fang Tsai and Vijaykrishnan Narayaynan and Yuan Xie and Mary Jane Irwin},
journal= {arXiv preprint arXiv:0710.4731},
year = {2011}
}
备注
Submitted on behalf of EDAA (http://www.edaa.com/)