Related papers: Trap-Enhanced Steep-Slope Negative-Capacitance FET…
As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…
Advancing complementary metal-oxide-semiconductor (CMOS) technology into the sub-1-nm angstr\"om-scale technology nodes is expected to involve alternative semiconductor channel materials, as silicon transistors encounter severe performance…
The study investigates the influence of negative capacitance on the transfer characteristics of vdW FETs on the heterophase of CIPS ferroelectric. Notably, a less pronounced NC resulting from the spatial distribution of the ferroelectric…
Defect engineering is a key strategy to control resistive switching (RS) in oxide-based memristive devices, where oxygen vacancy (OV) dynamics governs filament formation and rupture. We investigate the effect of Ag nanoparticles (AgNPs)…
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic…
Cryogenic field-effect transistors (FETs) offer great potential for a wide range of applications, the most notable example being classical control electronics for quantum information processors. In the latter context, on-chip FETs with low…
Atomically thin semiconductors have versatile future applications in the information and communication technologies for the ultimate miniaturization of electronic components. In particular, the ongoing research demands not only a…
Using self-consistent quantum transport simulation on realistic devices, we show that InAs band-to-band Tunneling Field Effect Transistors (TFET) with a heavily doped pocket in the gate-source overlap region can offer larger ON current and…
Non-volatile capacitive memories (nvCAPs) exhibiting AC small-signal capacitance on/off ratio (Con/Coff) with non-destructive read have emerged as a promising device for next-generation memory paradigms. Recently, BEOL-compatible…
A topological quantum field effect transistor (TQFET) uses electric field to switch a material from topological insulator ("on", with conducting edge states) to a conventional insulator ("off"), and can have low subthreshold swing due to…
As silicon-based devices continue to shrink to the nanoscale, traps at the Si-SiO$_2$ interface pose increasing challenges to device performance. These traps reduce channel carrier mobility and shift threshold voltages in integrated…
Density functional theory calculations for the electronic structures of the 4H-SiC(0001)/SiO$_2$ interface with atomic-scale steps are carried out to investigate the effect of NO annealing. The characteristic behavior of the conduction band…
A simple scalable scheme is reported for fabricating suspended carbon nanotube field effect transistors (CNT-FETs) without exposing pristine as-grown carbon nanotubes to subsequent chemical processing. Versatility and ease of the technique…
The photo-induced electron and hole transfer across the semiconductor-dielectric interface in trap dominated p-type organic field-effect transistors (OFETs) has been investigated. It has been observed that the transfer of electrons into the…
Two-dimensional (2D) semiconductors offer a promising prospect for high-performance and energy-efficient devices especially in the sub-10 nm regime. Inspired by the successful fabrication of 2D $\beta$-TeO$_2$ and the high on/off ratio and…
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…
We demonstrate a tunnel field effect transistor based on a lateral heterostructure patterned from an $\mathrm{LaAlO_3/SrTiO_3}$ electron gas. Charge is injected by tunneling from the $\mathrm{LaAlO_3}$/$\mathrm{SrTiO_3}$ contacts and the…
Electron-beam (e-beam) lithography is commonly used in fabricating metal-oxide-silicon (MOS) quantum devices but creates defects at the Si/SiO$_2$ interface. Here we show that a forming gas anneal is effective at removing shallow defects…
The performance of many superconducting devices is degraded in presence of non-equilibrium quasiparticles in the superconducting part. One promising approach towards their evacuation is the use of normal-metal quasiparticle traps, where…
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that…