Related papers: Trap-Enhanced Steep-Slope Negative-Capacitance FET…
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be…
We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional…
Amorphous oxide semiconductors are receiving significant attention due to their relevance for large area electronics. Their disordered microscopic structure causes the formation of band tails in the density of states (DOS) that strongly…
The Si/SiO$_2$ interface is populated by isolated trap states which modify its electronic properties. These traps are of critical interest for the development of semiconductor-based quantum sensors and computers, as well as nanoelectronic…
Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data…
This work reports back-end-of-line (BEOL) compatible, thin-film transistors (TFTs) with sub-10 nm tungsten-doped tin oxide (TWO) channels deposited by atomic layer deposition (ALD) at 150 $^\circ$C. TFTs with undoped SnO$_{\mathrm{x}}$,…
Fast-responding trap states introduced by NO-annealing are suspected to limit the channel mobility of 4H-SiC MOSFETs, yet their microscopic characterization remains challenging because conventional electrical methods are spatially averaged…
In this work, the effects of the duration of the post deposition annealing (PDA) in nitric oxide (NO) on the properties of SiO2/4H-SiC interfaces in n-channel lateral MOSFETs are investigated, with a special focus on the modifications of…
The transient negative capacitance (NC) of solid ferroelectric materials used in field effect transistors can reduce the power dissipation of electronics. Here we show that similar negative capacitance appears in the recently discovered…
In this work, we demonstrate enhancement-mode field-effect transistors by atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of…
3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device…
This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier…
This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier…
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on…
While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an…
Despite the enormous progress achieved during the past decade, nanoelectronic devices based on two-dimensional (2D) semiconductors still suffer from a limited electrical stability. This limited stability has been shown to result from the…
In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of…
Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…
High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate…
Modern microelectronic systems require long term operational stability, necessitating precise reliability models to predict device lifecycles and identify governing failure mechanisms. This is particularly critical for high power GaN…