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The scaling of Si transistor technology has resulted in a remarkable improvement in the performance of integrated circuits over the last decades. However, scaled transistors also require reduced electrical interconnect dimensions, which…

Most carbon nanotube field-effect transistors (CNTFETs) directly attach metal source/drain contacts to an intrinsic nanotube channel. When the gate oxide thickness is reduced, such transistors display strong ambipolar conduction, even when…

We report on the dielectric degradation of Rare-Earth Oxides (REOs), when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-Oxide-Semiconductor (MOS) devices with these…

We report spatially resolved optical probing of charge traps in organic field-effect transistors using focussed laser illumination. By scanning a 635 nm laser across the transistor channel and simultaneously acquiring transfer…

In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth), which…

Boltzmann tyranny poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative…

Negative capacitance (NC) in ferroelectrics, which stems from the imperfect screening of polarization, is considered a viable approach to lower voltage operation in the field-effect transistors (FETs) used in logic switches. In this paper,…

Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimizing the performances of…

Al$_{0.68}$Sc$_{0.32}$N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory…

Crystalline organic semiconductors, bonded by weak van der Waals forces, exhibit macroscopic properties that are very similar to those of inorganic semiconductors. While there are many open questions concerning the microscopic nature of…

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…

Organic semiconductors are usually not thought to show outstanding performance in highly-integrated, sub 100 nm transistors. Consequently, single-crystalline materials such as SWCNTs, MoS2 or inorganic semiconductors are the material of…

Under varying growth and device processing conditions, ultrabroadband photoconduction (UBPC) reveals strongly evolving trends in the defect density of states (DoS) for amorphous oxide semiconductor thin-film transistors (TFTs). Spanning the…

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…

Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport…

Ferroelectric field-effect transistors (FeFET) with two-dimensional (2D) semiconductor channels are promising low-power, embedded non-volatile memory (NVM) candidates for next-generation in-memory computing. However, the performance of…

An Al-AlO_x-Al single-electron transistor (SET) acting as the gate of a narrow (~ 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET) can induce a vertically aligned Si SET at the Si/SiO_2 interface near the MOSFET channel…

The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional…

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for…

The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the…