Related papers: SOT-MRAM Bitcell Scaling with BEOL Read Selectors:…

InGaZnO (IGZO) channel FeFETs have attracted notable interest thanks to their advances in endurance. This work evaluates the viability of NOR-type IGZO FeFETs for readcentric AI inference workloads via design-technology cooptimization…

As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ)…

SoCs are now designed with their own AI accelerator segment to accommodate the ever-increasing demand of Deep Learning (DL) applications. With powerful MAC engines for matrix multiplications, these accelerators show high computing…

For the past four decades, cost and features have driven CMOS scaling. Severe lithography and material limitations seen below the 20 nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to…

The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional…

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is an attractive alternative to current random access memory technologies due to its non-volatility, fast operation and high endurance. STT-MRAM does though have…

In this paper, we present a new 9T SRAM cell that has good write-ability and improves read stability at the same time. Simulation results show that the proposed design increases Read SNM (RSNM) and Ion/Ioff of read path by 219% and 113%,…

Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data…

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on…

This paper presents physical modeling and benchmarking for two-terminal spin-orbit torque magnetic random-access memory (2T-SOT-MRAM). The results indicate that the common SOT materials that provide only in-plane torque can provide little…

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a…

Analog crossbar arrays consisting of emerging memory devices can greatly alleviate the computational strain required by vector matrix multiplications for neural network applications. The ability to produce spin orbit torque-magnetic…

Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is…

The SRAM cell is made up of latch, which ensures that the cell data is preserved as long as power is turned on and refresh operation is not required for the SRAM cell. SRAM is widely used for on-chip cache memory in microprocessors, game…

Crossbar arrays using emerging non-volatile memory technologies such as Resistive RAM (ReRAM) offer high density, fast access speed and low-power. However the bandwidth of the crossbar is limited to single-bit read/write per access to avoid…

Compute-in-Read-Only-Memory (CiROM) accelerators offer outstanding energy efficiency for CNNs by eliminating runtime weight updates. However, their scalability to Large Language Models (LLMs) is fundamentally constrained by their vast…

We demonstrate approximate storage based on NAND-like spin-orbit torque (SOT) MRAM, through "device-modeling-architecture" explorations. We experimentally achieve down to 1E-5 level selectivity. Selectivity and low-power solutions are…

We demonstrate ultra-fast (down to 400 ps) bipolar magnetization switching of a three-terminal perpendicular Ta/FeCoB/MgO/FeCoB magnetic tunnel junction. The critical current density rises significantly as the current pulse shortens below…

In this paper, spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) devices are leveraged to realize sigmoidal neurons and binarized synapses for a single-cycle analog in-memory computing (IMC) architecture. First, an analog…

3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device…