Related papers: SOT-MRAM Bitcell Scaling with BEOL Read Selectors:…

Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to…

Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the…

Security and energy-efficiency are critical for computing applications in general and for edge applications in particular. Digital in-Memory Computing (IMC) in SRAM cells have widely been studied to accelerate inference tasks to maximize…

Last level caches (LLCs) occupy a large chip-area and there size is expected to grow further to offset the limitations of memory bandwidth and speed. Due to high leakage consumption of SRAM device, caches designed with SRAM consume large…

Spin-orbit torque (SOT) enables ultra-fast, energy-efficient magnetization switching, making it a promising mechanism for introducing MRAMs for cache memory applications. However, current SOT-MRAM devices face write efficiency limitations,…

The computing wall and data movement challenges of deep neural networks (DNNs) have exposed the limitations of conventional CMOS-based DNN accelerators. Furthermore, the deep structure and large model size will make DNNs prohibitive to…

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising emerging non-volatile memory (NVM) technology with wide applications. However, the data recovery of STT-MRAM is affected by the diversity of channel raw bit error…

Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost and high-density nonvolatile memory applications. As technology scales down to the single-nm regime, the increasing resistivity of…

The complementary field-effect transistors (CFETs), featuring vertically stacked n/p-FETs, enhance integration density and significantly reduce the area of standard cells such as static random-access memory (SRAM). However, the advantage of…

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders…

There is an extremely high demand for a high speed, low power, low leakage, and low noise Static Random-Access Memory (SRAM) for high performance cache memories. The energy efficiency of SRAM is of paramount importance in both high…

Increasing storage density exacerbates DRAM read disturbance, a circuit-level vulnerability exploited by system-level attacks. Unfortunately, existing defenses are either ineffective or prohibitively expensive. Efficient mitigation is…

Spin-Torque-Transfer RAM (STTRAM) is a promising technology however process variation poses serious challenge to sensing. To eliminate bit-to-bit process variation we propose a reference-less, destructive slope detection technique which…

This work presents a novel approach to configure 2T-nC ferroelectric RAM (FeRAM) for performing single cell logic-in-memory operations, highlighting its advantages in energy-efficient computation over conventional DRAM-based approaches.…

Scaling long-context ability is essential for Large Language Models (LLMs). To amortize the memory consumption across multiple devices in long-context training, inter-data partitioning (a.k.a. Data Parallelism) and intra-data partitioning…

Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure is attractive for nonvolatile, high-density, and low-latency storage-class memory applications. As technology scales down to the single-nm regime, the increasing…

Flash memories intended for SSD and mobile applications need to provide high random I/O performance. This requires using efficient schemes for reading small chunks of data (e.g. 0.5KB - 4KB) from random addresses. Furthermore, in order to…

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…

The deployment of intelligent reinforcement learning (RL) agents on resource-constrained edge devices remains a fundamental challenge due to the substantial memory, computational, and energy requirements of modern deep learning systems.…

Analog compute-in-memory (CIM) in static random-access memory (SRAM) is promising for accelerating deep learning inference by circumventing the memory wall and exploiting ultra-efficient analog low-precision arithmetic. Latest analog CIM…