Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array
Abstract
Crossbar arrays using emerging non-volatile memory technologies such as Resistive RAM (ReRAM) offer high density, fast access speed and low-power. However the bandwidth of the crossbar is limited to single-bit read/write per access to avoid selection of undesirable bits. We propose a technique to perform multi-bit read and write in a diode-STTRAM (Spin Transfer Torque RAM) crossbar array. Simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read and thus reduce the sneak path through the half-selected cells. In write operation, the half-selected cells are biased with a pulse voltage source which increases the write latency of these cells and enables to write 2-bits while keeping the half-selected bits undisturbed. Simulation results indicate biasing the half-selected cells by 700mV can enable reading as much as 512-bits while sustaining 512x512 crossbar with 2.04 years retention. The 2-bit writing requires pulsing by 50mV to optimize energy.
Keywords
Cite
@article{arxiv.1606.00470,
title = {Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array},
author = {Mohammad Nasim Imtiaz Khan and Swaroop Ghosh and Radha Krishna Aluru and Rashmi Jha},
journal= {arXiv preprint arXiv:1606.00470},
year = {2016}
}