Related papers: An FPGA-based readout chip emulator for the CMS ET…

This paper presents a readout system designed for testing the prototype of Small-Strip Thin Gap Chamber (sTGC), which is one of the main detector technologies used for ATLAS New-Small-Wheel Upgrade. This readout system aims at testing one…

An eight chip InGrid module has been tested as readout of a prototype time projection chamber. The construction of the modules as well as first preliminary results are presented. The InGrids, a Micromegas like amplification structure with a…

The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory systems where CPU access to various endpoints differs in…

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna…

The Beijing Spectrometer III (BESIII) endcap Time-Of-Filght (ETOF) was proposed to upgrade with Multigap Resistive Plate Chamber (MRPC) technology to substitute the current ETOF of scintillator+PMT for extending time resolutin better than…

In preparation of the operation of the CMS electromagnetic calorimeter (ECAL) barrel at the High Luminosity Large Hadron Collider (HL-LHC) the entire on-detector electronics will be replaced. The new readout electronics comprises 12240 very…

The TRB hardware module is a multi-purpose Trigger and Readout Board with on-board DAQ functionality developed for the upgrade of the HADES experiment. It contains a single computer chip (Etrax) running Linux as a well as a 100 Mbit/s…

As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper proposes a methodology to…

With the upgrade of the RPCs [1]-[2] and the increase of its performances, the study and the optimization of the read-out panel is necessary in order to maintain the signal integrity and to reduce the intrinsic crosstalk. Through…

Gas Electron Multiplier (GEM) technology is being considered for the forward muon upgrade of the CMS experiment in Phase 2 of the CERN LHC. Its first implementation is planned for the GE1/1 system in the $1.5 < \mid\eta\mid < 2.2$ region of…

With the ultimate goal of developing a pixel-based readout for a TPC at the ILC, a GridPix readout system consisting of one Timepix3 chip with an integrated amplification grid was embedded in a prototype detector. The performance was…

The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel readout chip will be controlled with a single serial input stream at 160 Mbps and will send out data via four current mode logic…

For space-based astronomical observations, it is important to have a mechanism to capture the digital output from the standard detector for further on-board analysis and storage. We have developed a generic (application- wise)…

We present an evaluation of a novel on-chip charge detector, called the Single electron Sensitive Read Out (SiSeRO), for charge-coupled device (CCD) image sensor applications. It uses a p-MOSFET transistor at the output stage with a…

The entire CMS silicon pixel detector will be replaced to operate at the High-Luminosity LHC. In this contribution, the new Tracker Endcap Pixel detector will be presented, focusing on a novel concept to provide both power and data…

This paper describes a step by step approach for implementing a scalable and run-time adaptable multi-standard packet detector for orthogonal frequency divisional multiplexing (OFDM) based communication standards. The paper briefly…

FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system…

We have developed a dedicated front-end-electronics board for a high-pressure xenon gas time projection chamber for a neutrinoless double-beta decay search. The ionization signal is readout by detecting electroluminescence photons with…

This contribution investigates a prototype of a TPC readout with a highly pixelated CMOS ASIC, which is an option for charged particles tracking of the ILC. A triple GEM stack was joined with a TimePix and MediPix2 chip (pixel size of…

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed…