Related papers: An FPGA-based readout chip emulator for the CMS ET…

The ALICE Collaboration is planning a major upgrade of its central barrel detectors to be able to cope with the increased LHC luminosity beyond 2020. For the TPC, this implies a replacement of the currently used gated MWPCs (Multi-Wire…

The prototype of time digitizing system for the upgrade of BESIII endcap TOF (ETOF) is introduced in this paper. The ETOF readout electronics has a formation of distributed architecture that hit signal from multi-gap resistive plate chamber…

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity…

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

A large Time Projection Chamber (TPC) is the main device for tracking and charged-particle identification in the ALICE experiment at the CERN LHC. After the second long shutdown in 2019-2020, the LHC will deliver Pb beams colliding at an…

This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the…

T0 detector, based on Multi-gap Resistive Plate Chambers (MRPC) technology, is one of the key components in the External Target Experiment. Through precision measurements of the MRPC signals, timing of the beam impact on target can be…

We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit Ethernet. In this…

Particle physics detectors increasingly make use of custom FPGA firmware and application-specific integrated circuits (ASICs) for data readout and triggering. As these designs become more complex, it is important to ensure that they are…

The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the…

The CMS GEM collaboration is considering Gas Electron Multipliers (GEMs) for upgrading the CMS forward muon system in the 1.5<|eta|<2.4 endcap region. GEM detectors can provide precision tracking and fast trigger information. They would…

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other…

This paper reports the PC implementation of a real-time simulator for testing protective relays, based on the widely used EMTP-ATP software. The proposed simulator was implemented using the GNU/Linux OS with a real-time kernel. In order to…

Semiconductor companies have increasingly adopted a methodology that starts with a system-level design specification in C/C++/SystemC. This model is extensively simulated to ensure correct functionality and performance. Later, a Register…

The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate.…

A new field programmable gate array (FPGA)-based emulation platform is proposed to accelerate fault tolerance analysis of inference accelerators of convolutional neural networks (CNN). For a given CNN model, hardware accelerator…

This article presents the readout electronics of a novel beam monitoring system for ion research facility accelerator. The readout electronics are divided into Front-end Card (FEC) and Readout Control Unit (RCU). FEC uses Topmetal II minus…

The ILD concept, one of two proposed detector concepts for the planned International Linear Collider (ILC), foresees a Time Projection Chamber (TPC) as the main tracking detector. The LCTPC (Linear Collider TPC) collaboration pursues R&D to…

Problem Statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important…