The TRB hardware module is a multi-purpose Trigger and Readout Board with on-board DAQ functionality developed for the upgrade of the HADES experiment. It contains a single computer chip (Etrax) running Linux as a well as a 100 Mbit/s Ethernet interface. It has been orginally designed to work as a 128-channel Time to Digital Converter based on the HPTDC chip from CERN. The new version contains a 2 Gbit/s optical link and an interface connector (15 Gbit/s) in order to realize an add-on card concept which makes the hardware very flexible. Moreover, an FPGA chip (Xilinx, Virtex 4 LX 40) and a TigerSharc DSP provide new computing resources which can be used to run on-line analysis algorithms. The TRB is proposed as a prototype for new modules for the planned detector systems PANDA and CBM at the future FAIR facility at GSI-Darmstadt.
@article{arxiv.0810.4723,
title = {The TRB for HADES and FAIR experiments at GSI},
author = {W. Krzemien and I. Frohlich and M. Kajetanowicz and K. Korcyl and J. Michel and M. Palka and P. Salabura and C. Schrader and P. Skott and H. Strobele and J. Stroth and A. Tarantola and M. Traxler and R. Trebacz},
journal= {arXiv preprint arXiv:0810.4723},
year = {2008}
}
Comments
Presented at 10th ICATPP Conference on Astroparticle, Particle and Space Physics, Detectors and Medical Physics Applications, Villa Olmo, Como, 8-12 October 2007 5 pages, 2 figures