Related papers: An FPGA-based readout chip emulator for the CMS ET…

Training of convolutional neural networks (CNNs)on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hard-ware is much more challenging than inference hardware, due to…

Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with traditional FPGA platforms. However, the limited eFPGA logic and…

Machine Learning (ML) has recently been a skyrocketing field in Computer Science. As computer hardware engineers, we are enthusiastic about hardware implementations of popular software ML architectures to optimize their performance,…

For the International Large Detector (ILD) at the planned International Linear Collider (ILC) a Time Projection Chamber (TPC) is foreseen as the main tracking detector. To achieve the required point resolution, Micro-Pattern Gaseous…

The challenging conditions of the High-Luminosity LHC require tailored hardware designs for the trigger and data acquisition systems. The Apollo platform features a "Service Module" with a powerful system-on-module computer that provides…

We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of $100\times100~\mu \text{m}^2$, where the sensors are Low Gain…

At SRON we have been developing X-ray TES micro-calorimeters as backup technology for the X-ray Integral Field Unit (X-IFU) of the Athena mission, demonstrating excellent resolving powers both under DC and AC bias. We also developed a…

We have operated a Medipix2 CMOS readout chip, with amplifying, shaping and charge discriminating front-end electronics integrated on the pixel-level, as a highly segmented direct charge collecting anode in a three-stage gas electron…

The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of…

We report on the design and test results of a prototype processor for the CMS Level-1 trigger that performs 3-D track reconstruction and measurement from data recorded by the cathode strip chambers of the endcap muon system. The tracking…

The ALICE experiment at the Large Hadron Collider at CERN is upgrading its central tracking detector, the Time Projection Chamber (TPC). The installation is foreseen during the second long shutdown of the Large Hadron Collider. The upgrade…

The LHC will undergo a major upgrade starting in 2025 towards the High Luminosity LHC (HL-LHC) to increase the instantaneous luminosity by a factor of 5 to 7 compared to the nominal value. The Phase-II Upgrade (2025-2027) will require the…

Due to the scaling problem of the DRAM technology, non-volatile memory devices, which are based on different principle of operation than DRAM, are now being intensively developed to expand the main memory of computers. Disaggregated memory…

In the framework of the High Luminosity LHC upgrade program, the CMS muon group built several different RPC prototypes that are now under test at the new CERN Gamma Irradiation Facility (GIF++). A dedicated Detector Control System has been…

In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation…

In this paper we describe the performance of a prototype of the High Angle Time Projection Chambers (HA-TPCs) that are being produced for the Near Detector (ND280) upgrade of the T2K experiment. The two HA-TPCs of ND280 will be instrumented…

Development of readout electronics for Time Projection Chamber for a Linear Collider is ongoing under stringent requirements on high channel density, lowest possible power consumption and small material budget. In the studied TPC readout…

In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog…

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential…

It is proposed to upgrade the endcap time-of-flight (ETOF) of the Beijing Spectrometer III (BESIII) with multi-gap resistive plate chamber (MRPC), aiming at overall time resolution about 80 ps. After the entire electronics system is ready,…