This paper describes a step by step approach for implementing a scalable and run-time adaptable multi-standard packet detector for orthogonal frequency divisional multiplexing (OFDM) based communication standards. The paper briefly describes considerations and design choices in making a modular system block with generic control supporting rapid prototyping and implementation of preamble-based packet detectors. The results were generated through implementation on a Xilinx Virtex-6 FPGA with a MicroBlaze processor instantiated to provide run-time control and adaptability.
@article{arxiv.1611.05787,
title = {FPGA Implementation of a Scalable and Run-Time Adaptable Multi-Standard Packet Detector},
author = {James Chacko and Marko Jacovic and Nagarajan Kandasamy and Kapil R. Dandekar},
journal= {arXiv preprint arXiv:1611.05787},
year = {2016}
}