Related papers: A New Design for Array Multiplier with Trade off i…

Increasing the number of transmit and receive elements in multiple-input-multiple-output (MIMO) antenna arrays imposes a substantial increase in hardware and computational costs. We mitigate this problem by employing a reconfigurable MIMO…

The logarithmic and anti-logarithmic converters are realized with the piecewise linear approximation method, which is implemented by the shift-and-add architecture. This brief utilizes the similarities of Log and Antilog functions so that…

This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. By integrating a…

This brief addresses the problem of implementing very large constant multiplications by a single variable under the shift-adds architecture using a minimum number of adders/subtractors. Due to the intrinsic complexity of the problem, we…

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable…

Theoretically, the three-dimensional (3D) array architecture provides a higher communication degree of freedom (DoF) compared to the planar arrays, allowing for greater capacity potential in multiple-input multiple-output (MIMO) systems.…

A method to reduce the transit time of majority of carriers in photomixers and photo detectors to $< 1$ ps is proposed. Enhanced optical fields associated with surface plasmon polaritons, coupled with velocity overshoot phenomenon results…

This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is…

We present a novel time-domain chromatic dispersion equalizer, implemented on FPGA, eliminating pre-processing and multipliers, achieving up to 54.3% energy savings over 80-1280 km with a simple, low-power design.

Memristive Processing In-Memory (PIM) is one of the promising techniques for overcoming the Von-Neumann bottleneck. Reduction of data transfer between processor and memory and data processing by memristors in data-intensive applications…

This work explores the consequences of introducing a piezoelectric gate barrier in a normal field-effect transistor. Because of the positive feedback of strain and piezoelectric charge, internal charge amplification occurs in such an…

In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence some number of general-purpose binary multipliers. The…

Contrary to the vast majority of works on simultaneous wireless information and power transfer that provide information-theoretic limits for the separate receiver architecture, in this work we focus on the integrated receiver and provide a…

As transistor sizes reach the mesoscopic scale, the limitations of traditional methods in ensuring thermodynamic consistency have made power dissipation optimization in transistor amplifiers a critical challenge. Based on stochastic…

This paper explores whether or not a complete ternary full adder, whose input variables can independently be '0', '1', or '2', is indispensable in the arithmetic blocks of adder, subtractor, and multiplier. Our investigations show that none…

The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper conducts a review of TFAs so that one can be familiar with the…

Transformers have revolutionized deep learning with applications in natural language processing, computer vision, and beyond. However, their computational demands make it challenging to deploy them on low-power edge devices. This paper…

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO)…

We consider a two-hop Multiple-Input Multiple-Output channel with a source, a single Amplify and Forward relay, and the destination. We consider the problem of designing precoders at the source and the relay, and the receiver matrix at the…

Large array-based transmission uses the combination of a massive number of antenna elements and clever precoder designs to achieve array gain and spatially multiplex different users. These precoders require linear front-ends, and more…