English

FPGA Implementation of Low-Power Multiplierless Pre-Processing Free Chromatic Dispersion Equalizer

Signal Processing 2024-12-24 v1

Abstract

We present a novel time-domain chromatic dispersion equalizer, implemented on FPGA, eliminating pre-processing and multipliers, achieving up to 54.3% energy savings over 80-1280 km with a simple, low-power design.

Cite

@article{arxiv.2412.17536,
  title  = {FPGA Implementation of Low-Power Multiplierless Pre-Processing Free Chromatic Dispersion Equalizer},
  author = {Geraldo Gomes and Pedro Freire and Jaroslaw E. Prilepsky and Sergei K. Turitsyn},
  journal= {arXiv preprint arXiv:2412.17536},
  year   = {2024}
}

Comments

Paper Accepted at OFC 2025

R2 v1 2026-06-28T20:46:36.248Z