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FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

Signal Processing 2022-12-08 v1 Information Theory Machine Learning math.IT Machine Learning
Authors: Keren Liu , Erik Börjeson , Christian Häger , Per Larsson-Edefors
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Abstract

We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.

Keywords

hardware acceleration machine learning

Cite

@article{arxiv.2212.03515,
  title  = {FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training},
  author = {Keren Liu and Erik Börjeson and Christian Häger and Per Larsson-Edefors},
  journal= {arXiv preprint arXiv:2212.03515},
  year   = {2022}
}

Comments

To be presented at the 2023 Optical Fiber Communication Conference (OFC)

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R2 v1 2026-06-28T07:24:32.417Z