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Real-Time FPGA Demonstrator of ANN-Based Equalization for Optical Communications

Signal Processing 2024-02-26 v1 Machine Learning
Authors: Jonas Ney , Patrick Matalla , Vincent Lauinger , Laurent Schmalen , Sebastian Randel , Norbert Wehn
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Abstract

In this work, we present a high-throughput field programmable gate array (FPGA) demonstrator of an artificial neural network (ANN)-based equalizer. The equalization is performed and illustrated in real-time for a 30 GBd, two-level pulse amplitude modulation (PAM2) optical communication system.

Keywords

hardware acceleration

Cite

@article{arxiv.2402.15288,
  title  = {Real-Time FPGA Demonstrator of ANN-Based Equalization for Optical Communications},
  author = {Jonas Ney and Patrick Matalla and Vincent Lauinger and Laurent Schmalen and Sebastian Randel and Norbert Wehn},
  journal= {arXiv preprint arXiv:2402.15288},
  year   = {2024}
}

Comments

Accepted and to be presented as demonstrator at the IEEE International Conference on Machine Learning for Communication and Networking (ICMLCN) 2024

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R2 v1 2026-06-28T14:58:17.653Z