Related papers: High Speed Multiple Valued Logic Full Adder Using …

The in-memory computing paradigm with emerging memory devices has been recently shown to be a promising way to accelerate deep learning. Resistive processing unit (RPU) has been proposed to enable the vector-vector outer product in a…

In recent years, neuromorphic computing has gained attention as a promising approach to enhance computing efficiency. Among existing approaches, neurotransistors have emerged as a particularly promising option as they accurately represent…

This study presents the implementation of an all-optical binary logic half adder by employing triple core photonic crystal fiber (TPCF). The noteworthy feature of the present investigation is that an identical set of TPCF schemes, which…

While nanoscale electronic logic circuits are well-established, the development of na-noscale thermal logic circuits has been slow, mainly due to the absence of efficient and controllable nonvolatile field-effect thermal transistors. In…

Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit implements only…

In February this year Google proposed a new Transformer variant called FLASH, which has a faster speed, lower VRAM footprint and better performance. This is achieved by designing a performant layer named GAU (Gated Attention Unit), which…

Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…

Fully Homomorphic Encryption (FHE) is a set of powerful cryptographic schemes that allows computation to be performed directly on encrypted data with an unlimited depth. Despite FHE's promising in privacy-preserving computing, yet in most…

Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing…

Reversible logic has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its applications in low power CMOS design, cryptography, optical information processing and…

Researchers and designers are facing problems with memory and power walls, considering the pervasiveness of Von-Neumann architecture in the design of processors and the problems caused by reducing the dimensions of deep sub-micron…

Catalyst design is crucial for materials synthesis, especially for complex reaction networks. Strategies like collaborative catalytic systems and multifunctional catalysts are effective but face challenges at the nanoscale. Carbon nanotube…

This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge AI applications. A novel Plus One Adder design is proposed as an incremental adder in…

Carbon nanotube field-effect transistors (CNT FETs) are regarded as promising candidates for next-generation energy-efficient computing systems. While research has employed the lift-off process to demonstrate the performance of CNT FETs,…

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density…

We set new speed records for multiplying long polynomials over finite fields of characteristic two. Our multiplication algorithm is based on an additive FFT (Fast Fourier Transform) by Lin, Chung, and Huang in 2014 comparing to previously…

The MALTA CMOS monolithic silicon pixel sensors has been developed in the Tower 180 nm CMOS imaging process. It includes an asynchronous readout scheme and complies with the ATLAS inner tracker requirements for the HL-LHC. Several 4-chip…

We present quantum simulations of carbon nanotube field-effect transistors (CNT-FETs) based on top-gated architectures and compare to electrical characterization on devices with 15 nm channel lengths. A non-equilibrium Green's function…

A robust power gating design using Graphene Nano-Ribbon Field Effect Transistors (GNRFET) is proposed using 16nm technology. The Power Gating (PG) structure is composed of GNRFET as a power switch and MOS power gated module. The proposed…

The thesis investigates the utilization of memristive and memcapacitive crossbar arrays in low-power machine learning accelerators, offering a comprehensive co-design framework for deep neural networks (DNN). The model, implemented through…