Related papers: High Speed Multiple Valued Logic Full Adder Using …

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision…

The continued evolution of CMOS technology demands materials and architectures that emphasize low power consumption, particularly for computations involving large scale data processing and multivariable optimization. Ferroelectric materials…

In Carry Propagate Adders, carry propagation is the critical delay. For the 1-digit adders that they use, the most efficient scheme is to generate two intermediate carries: C$_{out0}$ ($C_{in}$=0) and $C_{out1}$($C_{in}$=1). Then multiplex…

Short channel (~80 nm) n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) with potassium (K) doped source and drain regions and high-k gate dielectrics (ALD HfO2) are obtained. For nanotubes with diameter ~ 1.6 nm…

Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in…

Two-dimensional (2D) semiconductors offer a promising prospect for high-performance and energy-efficient devices especially in the sub-10 nm regime. Inspired by the successful fabrication of 2D $\beta$-TeO$_2$ and the high on/off ratio and…

This research introduces an FPGA-based hardware accelerator to optimize the Singular Value Decomposition (SVD) and Fast Fourier transform (FFT) operations in AI models. The proposed design aims to improve processing speed and reduce…

CMOS-transistors circuits have been used as a conventional approach for designing an analog multiplier in modern era of industrial electronics. However, previous studies have shown, that based on the working region of transistors, such as…

We present a novel low latency CMOS hardware accelerator for fully connected (FC) layers in deep neural networks (DNNs). The FC accelerator, FC-ACCL, is based on 128 8x8 or 16x16 processing elements (PEs) for matrix-vector multiplication,…

Triple Modular Redundancy (TMR) has been traditionally used to ensure complete tolerance to a single fault or a faulty processing unit, where the processing unit may be a circuit or a system. However, TMR incurs more than 200% overhead in…

Semiconductor optical amplifiers (SOA) are a fundamental building block for many photonic systems. However, their power inefficiency has been setting back operational cost reduction, and the resulting thermal losses constrain…

Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial…

We demonstrate high yield fabrication of field effect transistors (FET) using chemically reduced graphene oxide (RGO) sheets suspended in water assembled via dielectrophoresis. The two terminal resistances of the devices were improved by an…

In view of the large amount of calculation and long calculation time of convolutional neural network (CNN), this paper proposes a convolutional neural network hardware accelerator based on field programmable logic gate array (FPGA). First,…

Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones,…

Nanosized energy storage, energy-harvesting, and functional devices are the three key components for integrated self-power systems. Here, we report on nanoscale electrochemical devices with a nearly three-fold enhanced stored charge under…

The proliferation of Transformer models is often constrained by the significant computational and memory bandwidth demands of deployment. To address this, we present MXFormer, a novel, hybrid, weight-stationary Compute-in-Memory (CIM)…

In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution…

Indium-Arsenide (InAs) nanowire field-effect transistors (NWFETs) are promising platforms for high-speed, low-power nanoelectronics operating at cryogenic conditions, relevant for quantum information processing. We use selective area growth…

We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization…