Hypervisor Extension for a RISC-V Processor
Hardware Architecture
2024-06-27 v1
Authors:
Jaume Gauchola
, JuanJosé Costa
, Enric Morancho
, Ramon Canal
, Xavier Carril
, Max Doblas
, Beatriz Otero
, Alex Pajuelo
, Eva Rodríguez
, Javier Salamero
, Javier Verdú
Abstract
This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.
Cite
@article{arxiv.2406.17796,
title = {Hypervisor Extension for a RISC-V Processor},
author = {Jaume Gauchola and JuanJosé Costa and Enric Morancho and Ramon Canal and Xavier Carril and Max Doblas and Beatriz Otero and Alex Pajuelo and Eva Rodríguez and Javier Salamero and Javier Verdú},
journal= {arXiv preprint arXiv:2406.17796},
year = {2024}
}
Comments
RISC-V Summit Europe 2023, June 5-9, 2023
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