Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

Andreas Olofsson

Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

Hardware Architecture 2016-10-07 v1

Authors: Andreas Olofsson

Abstract

This paper describes the design of a 1024-core processor chip in 16nm FinFet technology. The chip ("Epiphany-V") contains an array of 1024 64-bit RISC processors, 64MB of on-chip SRAM, three 136-bit wide mesh Networks-On-Chip, and 1024 programmable IO pins. The chip has taped out and is being manufactured by TSMC. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.

Keywords

computer architecture fpga accelerator

Cite

@article{arxiv.1610.01832,
  title  = {Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip},
  author = {Andreas Olofsson},
  journal= {arXiv preprint arXiv:1610.01832},
  year   = {2016}
}

Comments

15 pages, 7 figures

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